[u-boot.git] / drivers / clk / rockchip / clk_rk322x.c

/*
 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <errno.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk322x.h>
#include <asm/arch/hardware.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <linux/log2.h>

DECLARE_GLOBAL_DATA_PTR;

enum {
	VCO_MAX_HZ	= 3200U * 1000000,
	VCO_MIN_HZ	= 800 * 1000000,
	OUTPUT_MAX_HZ	= 3200U * 1000000,
	OUTPUT_MIN_HZ	= 24 * 1000000,
};

#define RATE_TO_DIV(input_rate, output_rate) \
	((input_rate) / (output_rate) - 1);

#define DIV_TO_RATE(input_rate, div)	((input_rate) / ((div) + 1))

#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
	.refdiv = _refdiv,\
	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
			 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
			 #hz "Hz cannot be hit with PLL "\
			 "divisors on line " __stringify(__LINE__));

/* use integer mode*/
static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);

static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
			 const struct pll_div *div)
{
	int pll_id = rk_pll_id(clk_id);
	struct rk322x_pll *pll = &cru->pll[pll_id];

	/* All PLLs have same VCO and output frequency range restrictions. */
	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;

	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
	      pll, div->fbdiv, div->refdiv, div->postdiv1,
	      div->postdiv2, vco_hz, output_hz);
	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	       output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);

	/* use integer mode */
	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
	/* Power down */
	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);

	rk_clrsetreg(&pll->con0,
		     PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
		     (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
		     (div->postdiv2 << PLL_POSTDIV2_SHIFT |
		     div->refdiv << PLL_REFDIV_SHIFT));

	/* Power Up */
	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);

	/* waiting for pll lock */
	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
		udelay(1);

	return 0;
}

static void rkclk_init(struct rk322x_cru *cru)
{
	u32 aclk_div;
	u32 hclk_div;
	u32 pclk_div;

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK | APLL_MODE_MASK,
		     GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
		     APLL_MODE_SLOW << APLL_MODE_SHIFT);

	/* init pll */
	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);

	/*
	 * select apll as cpu/core clock pll source and
	 * set up dependent divisors for PERI and ACLK clocks.
	 * core hz : apll = 1:1
	 */
	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);

	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);

	rk_clrsetreg(&cru->cru_clksel_con[0],
		     CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
		     CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
		     0 << CORE_DIV_CON_SHIFT);

	rk_clrsetreg(&cru->cru_clksel_con[1],
		     CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
		     aclk_div << CORE_ACLK_DIV_SHIFT |
		     pclk_div << CORE_PERI_DIV_SHIFT);

	/*
	 * select apll as pd_bus bus clock source and
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);

	pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
	assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);

	hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
	assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);

	rk_clrsetreg(&cru->cru_clksel_con[0],
		     BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
		     BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
		     aclk_div << BUS_ACLK_DIV_SHIFT);

	rk_clrsetreg(&cru->cru_clksel_con[1],
		     BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
		     pclk_div << BUS_PCLK_DIV_SHIFT |
		     hclk_div << BUS_HCLK_DIV_SHIFT);

	/*
	 * select gpll as pd_peri bus clock source and
	 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
	 */
	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);

	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
	assert((1 << hclk_div) * PERI_HCLK_HZ ==
		PERI_ACLK_HZ && (hclk_div < 0x4));

	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
	assert((1 << pclk_div) * PERI_PCLK_HZ ==
		PERI_ACLK_HZ && pclk_div < 0x8);

	rk_clrsetreg(&cru->cru_clksel_con[10],
		     PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
		     PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
		     PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
		     pclk_div << PERI_PCLK_DIV_SHIFT |
		     hclk_div << PERI_HCLK_DIV_SHIFT |
		     aclk_div << PERI_ACLK_DIV_SHIFT);

	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con,
		     GPLL_MODE_MASK | APLL_MODE_MASK,
		     GPLL_MODE_NORM << GPLL_MODE_SHIFT |
		     APLL_MODE_NORM << APLL_MODE_SHIFT);
}

/* Get pll rate by id */
static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
				   enum rk_clk_id clk_id)
{
	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
	uint32_t con;
	int pll_id = rk_pll_id(clk_id);
	struct rk322x_pll *pll = &cru->pll[pll_id];
	static u8 clk_shift[CLK_COUNT] = {
		0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
		GPLL_MODE_SHIFT, 0xff
	};
	static u32 clk_mask[CLK_COUNT] = {
		0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
		GPLL_MODE_MASK, 0xff
	};
	uint shift;
	uint mask;

	con = readl(&cru->cru_mode_con);
	shift = clk_shift[clk_id];
	mask = clk_mask[clk_id];

	switch ((con & mask) >> shift) {
	case GPLL_MODE_SLOW:
		return OSC_HZ;
	case GPLL_MODE_NORM:

		/* normal mode */
		con = readl(&pll->con0);
		postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
		fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
		con = readl(&pll->con1);
		postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
		refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
		return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
	default:
		return 32768;
	}
}

static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
				  int periph)
{
	uint src_rate;
	uint div, mux;
	u32 con;

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
		con = readl(&cru->cru_clksel_con[11]);
		mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
		con = readl(&cru->cru_clksel_con[12]);
		div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		con = readl(&cru->cru_clksel_con[11]);
		mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
		div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
		break;
	default:
		return -EINVAL;
	}

	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
	return DIV_TO_RATE(src_rate, div);
}

static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
				  int periph, uint freq)
{
	int src_clk_div;
	int mux;

	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);

	/* mmc clock auto divide 2 in internal */
	src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;

	if (src_clk_div > 0x7f) {
		src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
		mux = EMMC_SEL_24M;
	} else {
		mux = EMMC_SEL_GPLL;
	}

	switch (periph) {
	case HCLK_EMMC:
	case SCLK_EMMC:
		rk_clrsetreg(&cru->cru_clksel_con[11],
			     EMMC_PLL_MASK,
			     mux << EMMC_PLL_SHIFT);
		rk_clrsetreg(&cru->cru_clksel_con[12],
			     EMMC_DIV_MASK,
			     (src_clk_div - 1) << EMMC_DIV_SHIFT);
		break;
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		rk_clrsetreg(&cru->cru_clksel_con[11],
			     MMC0_PLL_MASK | MMC0_DIV_MASK,
			     mux << MMC0_PLL_SHIFT |
			     (src_clk_div - 1) << MMC0_DIV_SHIFT);
		break;
	default:
		return -EINVAL;
	}

	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
}

static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
{
	struct pll_div dpll_cfg;

	/*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
	switch (set_rate) {
	case 400*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
		break;
	case 600*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
		break;
	case 800*MHz:
		dpll_cfg = (struct pll_div)
		{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
		break;
	}

	/* pll enter slow-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
	/* PLL enter normal-mode */
	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
		     DPLL_MODE_NORM << DPLL_MODE_SHIFT);

	return set_rate;
}
static ulong rk322x_clk_get_rate(struct clk *clk)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	ulong rate, gclk_rate;

	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	switch (clk->id) {
	case 0 ... 63:
		rate = rkclk_pll_get_rate(priv->cru, clk->id);
		break;
	case HCLK_EMMC:
	case SCLK_EMMC:
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
		break;
	default:
		return -ENOENT;
	}

	return rate;
}

static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
{
	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
	ulong new_rate, gclk_rate;

	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
	switch (clk->id) {
	case HCLK_EMMC:
	case SCLK_EMMC:
	case HCLK_SDMMC:
	case SCLK_SDMMC:
		new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
						clk->id, rate);
		break;
	case CLK_DDR:
		new_rate = rk322x_ddr_set_clk(priv->cru, rate);
		break;
	default:
		return -ENOENT;
	}

	return new_rate;
}

static struct clk_ops rk322x_clk_ops = {
	.get_rate	= rk322x_clk_get_rate,
	.set_rate	= rk322x_clk_set_rate,
};

static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
{
	struct rk322x_clk_priv *priv = dev_get_priv(dev);

	priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);

	return 0;
}

static int rk322x_clk_probe(struct udevice *dev)
{
	struct rk322x_clk_priv *priv = dev_get_priv(dev);

	rkclk_init(priv->cru);

	return 0;
}

static int rk322x_clk_bind(struct udevice *dev)
{
	int ret;

	/* The reset driver does not have a device node, so bind it here */
	ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev);
	if (ret)
		debug("Warning: No RK3036 reset driver: ret=%d\n", ret);

	return 0;
}

static const struct udevice_id rk322x_clk_ids[] = {
	{ .compatible = "rockchip,rk3228-cru" },
	{ }
};

U_BOOT_DRIVER(rockchip_rk322x_cru) = {
	.name		= "clk_rk322x",
	.id		= UCLASS_CLK,
	.of_match	= rk322x_clk_ids,
	.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
	.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
	.ops		= &rk322x_clk_ops,
	.bind		= rk322x_clk_bind,
	.probe		= rk322x_clk_probe,
};
Commit	Line	Data
045029cb KY	1	/*
	2	* (C) Copyright 2017 Rockchip Electronics Co., Ltd
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
	7	#include <common.h>
	8	#include <clk-uclass.h>
	9	#include <dm.h>
	10	#include <errno.h>
	11	#include <syscon.h>
	12	#include <asm/io.h>
	13	#include <asm/arch/clock.h>
	14	#include <asm/arch/cru_rk322x.h>
	15	#include <asm/arch/hardware.h>
	16	#include <dm/lists.h>
	17	#include <dt-bindings/clock/rk3228-cru.h>
	18	#include <linux/log2.h>
	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	enum {
	23	VCO_MAX_HZ = 3200U * 1000000,
	24	VCO_MIN_HZ = 800 * 1000000,
	25	OUTPUT_MAX_HZ = 3200U * 1000000,
	26	OUTPUT_MIN_HZ = 24 * 1000000,
	27	};
	28
	29	#define RATE_TO_DIV(input_rate, output_rate) \
	30	((input_rate) / (output_rate) - 1);
	31
	32	#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
	33
	34	#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
	35	.refdiv = _refdiv,\
	36	.fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
	37	.postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
	38	_Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
	39	OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
	40	#hz "Hz cannot be hit with PLL "\
	41	"divisors on line " __stringify(__LINE__));
	42
	43	/* use integer mode*/
	44	static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
	45	static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
	46
	47	static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
	48	const struct pll_div *div)
	49	{
	50	int pll_id = rk_pll_id(clk_id);
	51	struct rk322x_pll *pll = &cru->pll[pll_id];
	52
	53	/* All PLLs have same VCO and output frequency range restrictions. */
	54	uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
	55	uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
	56
	57	debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
	58	pll, div->fbdiv, div->refdiv, div->postdiv1,
	59	div->postdiv2, vco_hz, output_hz);
	60	assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
	61	output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
	62
	63	/* use integer mode */
	64	rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
65	/* Power down */
66	rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
67
68	rk_clrsetreg(&pll->con0,
69	PLL_POSTDIV1_MASK \| PLL_FBDIV_MASK,
70	(div->postdiv1 << PLL_POSTDIV1_SHIFT) \| div->fbdiv);
71	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK \| PLL_REFDIV_MASK,
72	(div->postdiv2 << PLL_POSTDIV2_SHIFT \|
73	div->refdiv << PLL_REFDIV_SHIFT));
74
75	/* Power Up */
76	rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
77
78	/* waiting for pll lock */
79	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
80	udelay(1);
81
82	return 0;
83	}
84
85	static void rkclk_init(struct rk322x_cru *cru)
86	{
87	u32 aclk_div;
88	u32 hclk_div;
89	u32 pclk_div;
90
91	/* pll enter slow-mode */
92	rk_clrsetreg(&cru->cru_mode_con,
93	GPLL_MODE_MASK \| APLL_MODE_MASK,
94	GPLL_MODE_SLOW << GPLL_MODE_SHIFT \|
95	APLL_MODE_SLOW << APLL_MODE_SHIFT);
96
97	/* init pll */
98	rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
99	rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
100
101	/*
102	* select apll as cpu/core clock pll source and
103	* set up dependent divisors for PERI and ACLK clocks.
104	* core hz : apll = 1:1
105	*/
106	aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
107	assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
108
109	pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
110	assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
111
112	rk_clrsetreg(&cru->cru_clksel_con[0],
113	CORE_CLK_PLL_SEL_MASK \| CORE_DIV_CON_MASK,
114	CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT \|
115	0 << CORE_DIV_CON_SHIFT);
116
117	rk_clrsetreg(&cru->cru_clksel_con[1],
118	CORE_ACLK_DIV_MASK \| CORE_PERI_DIV_MASK,
119	aclk_div << CORE_ACLK_DIV_SHIFT \|
120	pclk_div << CORE_PERI_DIV_SHIFT);
121
122	/*
123	* select apll as pd_bus bus clock source and
124	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
125	*/
126	aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
127	assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
128
129	pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
130	assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
131
132	hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
133	assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
134
135	rk_clrsetreg(&cru->cru_clksel_con[0],
136	BUS_ACLK_PLL_SEL_MASK \| BUS_ACLK_DIV_MASK,
137	BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT \|
138	aclk_div << BUS_ACLK_DIV_SHIFT);
139
140	rk_clrsetreg(&cru->cru_clksel_con[1],
141	BUS_PCLK_DIV_MASK \| BUS_HCLK_DIV_MASK,
142	pclk_div << BUS_PCLK_DIV_SHIFT \|
143	hclk_div << BUS_HCLK_DIV_SHIFT);
144
145	/*
146	* select gpll as pd_peri bus clock source and
147	* set up dependent divisors for PCLK/HCLK and ACLK clocks.
148	*/
149	aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
150	assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
151
152	hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
153	assert((1 << hclk_div) * PERI_HCLK_HZ ==
154	PERI_ACLK_HZ && (hclk_div < 0x4));
155
156	pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
157	assert((1 << pclk_div) * PERI_PCLK_HZ ==
158	PERI_ACLK_HZ && pclk_div < 0x8);
159
160	rk_clrsetreg(&cru->cru_clksel_con[10],
161	PERI_PLL_SEL_MASK \| PERI_PCLK_DIV_MASK \|
162	PERI_HCLK_DIV_MASK \| PERI_ACLK_DIV_MASK,
163	PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT \|
164	pclk_div << PERI_PCLK_DIV_SHIFT \|
165	hclk_div << PERI_HCLK_DIV_SHIFT \|
166	aclk_div << PERI_ACLK_DIV_SHIFT);
167
168	/* PLL enter normal-mode */
169	rk_clrsetreg(&cru->cru_mode_con,
170	GPLL_MODE_MASK \| APLL_MODE_MASK,
171	GPLL_MODE_NORM << GPLL_MODE_SHIFT \|
172	APLL_MODE_NORM << APLL_MODE_SHIFT);
173	}
174
175	/* Get pll rate by id */
176	static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
177	enum rk_clk_id clk_id)
178	{
179	uint32_t refdiv, fbdiv, postdiv1, postdiv2;
180	uint32_t con;
181	int pll_id = rk_pll_id(clk_id);
182	struct rk322x_pll *pll = &cru->pll[pll_id];
183	static u8 clk_shift[CLK_COUNT] = {
184	0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
185	GPLL_MODE_SHIFT, 0xff
186	};
187	static u32 clk_mask[CLK_COUNT] = {
188	0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
189	GPLL_MODE_MASK, 0xff
190	};
191	uint shift;
192	uint mask;
193
194	con = readl(&cru->cru_mode_con);
195	shift = clk_shift[clk_id];
196	mask = clk_mask[clk_id];
197
198	switch ((con & mask) >> shift) {
199	case GPLL_MODE_SLOW:
200	return OSC_HZ;
201	case GPLL_MODE_NORM:
202
203	/* normal mode */
204	con = readl(&pll->con0);
205	postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
206	fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
207	con = readl(&pll->con1);
208	postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
209	refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
210	return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
211	default:
212	return 32768;
213	}
214	}
215
216	static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
217	int periph)
218	{
219	uint src_rate;
220	uint div, mux;
221	u32 con;
222
223	switch (periph) {
224	case HCLK_EMMC:
225	case SCLK_EMMC:
226	con = readl(&cru->cru_clksel_con[11]);
227	mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
228	con = readl(&cru->cru_clksel_con[12]);
229	div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
230	break;
231	case HCLK_SDMMC:
232	case SCLK_SDMMC:
233	con = readl(&cru->cru_clksel_con[11]);
234	mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
235	div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
236	break;
237	default:
238	return -EINVAL;
239	}
240
241	src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
242	return DIV_TO_RATE(src_rate, div);
243	}
244
245	static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
246	int periph, uint freq)
247	{
248	int src_clk_div;
249	int mux;
250
251	debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
252
253	/* mmc clock auto divide 2 in internal */
254	src_clk_div = (clk_general_rate / 2 + freq - 1) / freq;
255
256	if (src_clk_div > 0x7f) {
257	src_clk_div = (OSC_HZ / 2 + freq - 1) / freq;
258	mux = EMMC_SEL_24M;
259	} else {
260	mux = EMMC_SEL_GPLL;
261	}
262
263	switch (periph) {
264	case HCLK_EMMC:
265	case SCLK_EMMC:
266	rk_clrsetreg(&cru->cru_clksel_con[11],
267	EMMC_PLL_MASK,
268	mux << EMMC_PLL_SHIFT);
269	rk_clrsetreg(&cru->cru_clksel_con[12],
270	EMMC_DIV_MASK,
271	(src_clk_div - 1) << EMMC_DIV_SHIFT);
272	break;
273	case HCLK_SDMMC:
274	case SCLK_SDMMC:
275	rk_clrsetreg(&cru->cru_clksel_con[11],
276	MMC0_PLL_MASK \| MMC0_DIV_MASK,
277	mux << MMC0_PLL_SHIFT \|
278	(src_clk_div - 1) << MMC0_DIV_SHIFT);
279	break;
280	default:
281	return -EINVAL;
282	}
283
284	return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
285	}
286
287	static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
288	{
289	struct pll_div dpll_cfg;
290
291	/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
292	switch (set_rate) {
293	case 400*MHz:
294	dpll_cfg = (struct pll_div)
295	{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
296	break;
297	case 600*MHz:
298	dpll_cfg = (struct pll_div)
299	{.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
300	break;
301	case 800*MHz:
302	dpll_cfg = (struct pll_div)
303	{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
304	break;
305	}
306
307	/* pll enter slow-mode */
308	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
309	DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
310	rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
311	/* PLL enter normal-mode */
312	rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
313	DPLL_MODE_NORM << DPLL_MODE_SHIFT);
314
315	return set_rate;
316	}
317	static ulong rk322x_clk_get_rate(struct clk *clk)
318	{
319	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
320	ulong rate, gclk_rate;
321
322	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
323	switch (clk->id) {
324	case 0 ... 63:
325	rate = rkclk_pll_get_rate(priv->cru, clk->id);
326	break;
327	case HCLK_EMMC:
328	case SCLK_EMMC:
329	case HCLK_SDMMC:
330	case SCLK_SDMMC:
331	rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
332	break;
333	default:
334	return -ENOENT;
335	}
336
337	return rate;
338	}
339
340	static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
341	{
342	struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
343	ulong new_rate, gclk_rate;
344
345	gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
346	switch (clk->id) {
347	case HCLK_EMMC:
348	case SCLK_EMMC:
349	case HCLK_SDMMC:
350	case SCLK_SDMMC:
351	new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
352	clk->id, rate);
353	break;
354	case CLK_DDR:
355	new_rate = rk322x_ddr_set_clk(priv->cru, rate);
356	break;
357	default:
358	return -ENOENT;
359	}
360
361	return new_rate;
362	}
363
364	static struct clk_ops rk322x_clk_ops = {
365	.get_rate = rk322x_clk_get_rate,
366	.set_rate = rk322x_clk_set_rate,
367	};
368
369	static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
370	{
371	struct rk322x_clk_priv *priv = dev_get_priv(dev);
372
373	priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
374
375	return 0;
376	}
377
378	static int rk322x_clk_probe(struct udevice *dev)
379	{
380	struct rk322x_clk_priv *priv = dev_get_priv(dev);
381
382	rkclk_init(priv->cru);
383
384	return 0;
385	}
386
387	static int rk322x_clk_bind(struct udevice *dev)
388	{
389	int ret;
390
391	/* The reset driver does not have a device node, so bind it here */
392	ret = device_bind_driver(gd->dm_root, "rk322x_sysreset", "reset", &dev);
393	if (ret)
394	debug("Warning: No RK3036 reset driver: ret=%d\n", ret);
395
396	return 0;
397	}
398
399	static const struct udevice_id rk322x_clk_ids[] = {
400	{ .compatible = "rockchip,rk3228-cru" },
401	{ }
402	};
403
404	U_BOOT_DRIVER(rockchip_rk322x_cru) = {
405	.name = "clk_rk322x",
406	.id = UCLASS_CLK,
407	.of_match = rk322x_clk_ids,
408	.priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
409	.ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
410	.ops = &rk322x_clk_ops,
411	.bind = rk322x_clk_bind,
412	.probe = rk322x_clk_probe,
413	};