Luiz Capitulino [Tue, 18 Feb 2014 14:08:14 +0000 (09:08 -0500)]
MAINTAINERS: update status for HMP, QAPI and QMP trees
This commit updates the status for the HMP, QAPI and QMP trees from
"Supported" to "Maintained".
In practice this means that patch review and pull requests may take
longer. Also, I'll rely more on reviewers such as Eric Blake so that
I'm able to send pull requests regularly.
Fam Zheng [Wed, 12 Feb 2014 03:05:13 +0000 (11:05 +0800)]
QMP: Allow dot separated dict path arguments in qmp-shell
As another convenience to allow using commands that expect a dict as
argument, this patch adds support for foo.bar=value syntax, similar to
command line argument style:
Peter Maydell [Wed, 26 Feb 2014 22:53:50 +0000 (22:53 +0000)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140226' into staging
target-arm queue:
* fixes for various Coverity-spotted bugs
* support new KVM device control API for VGIC
* support KVM VGIC save/restore/migration
* more AArch64 system mode foundations
* support ARMv8 CRC instructions for A32/T32
* PL330 minor fixes and cleanup
# gpg: Signature made Wed 26 Feb 2014 17:51:32 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <[email protected]>"
* remotes/pmaydell/tags/pull-target-arm-20140226: (45 commits)
dma/pl330: implement dmaadnh instruction
dma/pl330: Fix buffer depth
dma/pl330: Add event debugging printfs
dma/pl330: Rename parent_obj
dma/pl330: printf format type sweep.
dma/pl330: Fix misleading type
dma/pl330: Delete overly verbose debug printf
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
include/qemu/crc32c.h: Rename include guards to match filename
target-arm: Add utility function for checking AA32/64 state of an EL
target-arm: Implement AArch64 view of CPACR
target-arm: A64: Implement MSR (immediate) instructions
target-arm: Store AIF bits in env->pstate for AArch32
target-arm: A64: Implement WFI
target-arm: Get MMU index information correct for A64 code
target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
target-arm: Implement AArch64 dummy breakpoint and watchpoint registers
target-arm: Implement AArch64 ID and feature registers
target-arm: Implement AArch64 generic timers
target-arm: Implement AArch64 MPIDR
...
Peter Maydell [Wed, 26 Feb 2014 20:04:37 +0000 (20:04 +0000)]
Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into staging
Net patches
# gpg: Signature made Tue 25 Feb 2014 13:32:33 GMT using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <[email protected]>"
# gpg: aka "Stefan Hajnoczi <[email protected]>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/net-pull-request:
virtio-net: use qemu_get_queue() where possible
vhost_net: use offload API instead of bypassing it
net: remove implicit peer from offload API
net: Disable netmap backend when not supported
net: add offloading support to netmap backend
net: make tap offloading callbacks static
net: virtio-net and vmxnet3 use offloading API
net: TAP uses NetClientInfo offloading callbacks
net: extend NetClientInfo for offloading
net: change vnet-hdr TAP prototypes
opencores_eth: flush queue whenever can_receive can go from false to true
Bandan Das [Wed, 26 Feb 2014 17:33:45 +0000 (10:33 -0700)]
vfio: blacklist loading of unstable roms
Certain cards such as the Broadcom BCM57810 have rom quirks
that exhibit unstable system behavior duing device assignment. In
the particular case of 57810, rom execution hangs and if a FLR
follows, the device becomes inoperable until a power cycle. This
change blacklists loading of rom for such cards unless the user
specifies a romfile or rombar=1 on the cmd line
Bandan Das [Wed, 26 Feb 2014 17:32:40 +0000 (10:32 -0700)]
qdev-monitor: set DeviceState opts before calling realize
Setting opts before the realize property is set allows the
following patch to make decisions based on whether the user
specified "rombar". This also avoids having to create a new
tristate property especially for this purpose
vfio: Fix overrun after readlink() fills buffer completely
readlink() returns the number of bytes written to the buffer, and it
doesn't write a terminating null byte. vfio_init() writes it itself.
Overruns the buffer when readlink() filled it completely.
Fix by treating readlink() filling the buffer completely as error,
like we do in pci-assign.c's assign_failed_examine().
Implement the missing DMAADNH instruction. This is a minor variant
of the DMAADDH instruction, so factor out to a common implementation
for both (dmaadxh).
This is the product of the data-width and the depth arguments, I.e the
depth of the FIFO is in terms of data entries and not bytes (which is
what the original implementation was suggesting). Fix.
Use PRI formats as appropriate rather than raw %x and %d. This fixes
debug printfery on some host platforms. Fix types of debug only
variables as appropriate.
This type really should just be a regular int as no usages rely on it's
32 bitness (it's only meaningful as a bit position and not a bit mask).
This also fixes a printf which uses the variable with a regular %d.
Will Newton [Wed, 26 Feb 2014 17:20:07 +0000 (17:20 +0000)]
target-arm: Add support for AArch32 ARMv8 CRC32 instructions
Add support for AArch32 CRC32 and CRC32C instructions added in ARMv8
and add a CPU feature flag to enable these instructions.
The CRC32-C implementation used is the built-in qemu implementation
and The CRC-32 implementation is from zlib. This requires adding zlib
to LIBS to ensure it is linked for the linux-user binary.
Peter Maydell [Wed, 26 Feb 2014 17:20:07 +0000 (17:20 +0000)]
target-arm: Add utility function for checking AA32/64 state of an EL
There are various situations where we need to behave differently
depending on whether a given exception level is in AArch64 or
AArch32 state. The state of the current exception level is stored
in env->aarch64, but there's no equivalent guest-visible architected
state bits for the status of the exception levels "above" the
current one which may still affect execution. At the moment we
only support EL1 (ie no EL2 or EL3) and insist that AArch64
capable CPUs run with EL1 in AArch64 state, but these may change
in the future, so abstract out the "what state is this?" check
into a utility function which can be enhanced later if necessary.
Peter Maydell [Wed, 26 Feb 2014 17:20:06 +0000 (17:20 +0000)]
target-arm: Implement AArch64 view of CPACR
Implement the AArch64 view of the CPACR. The AArch64
CPACR is defined to have a lot of RES0 bits, but since
the architecture defines that RES0 bits may be implemented
as reads-as-written and we know that a v8 CPU will have
no registered coprocessors for cp0..cp13 we can safely
implement the whole register this way.
Peter Maydell [Wed, 26 Feb 2014 17:20:06 +0000 (17:20 +0000)]
target-arm: Store AIF bits in env->pstate for AArch32
To avoid complication in code that otherwise would not need to
care about whether EL1 is AArch32 or AArch64, we should store
the interrupt mask bits (CPSR.AIF in AArch32 and PSTATE.DAIF
in AArch64) in one place consistently regardless of EL1's mode.
Since AArch64 has an extra enable bit (D for debug exceptions)
which isn't visible in AArch32, this means we need to keep
the enables in env->pstate. (This is also consistent with the
general approach we're taking that we handle 32 bit CPUs as
being like AArch64/ARMv8 CPUs but which only run in 32 bit mode.)
Peter Maydell [Wed, 26 Feb 2014 17:20:06 +0000 (17:20 +0000)]
target-arm: A64: Implement WFI
Implement the WFI instruction for A64; this just involves wiring
up the instruction, and adding a gen_a64_set_pc_im() which was
accidentally omitted from the A64 decoder top loop.
Peter Maydell [Wed, 26 Feb 2014 17:20:05 +0000 (17:20 +0000)]
target-arm: Get MMU index information correct for A64 code
Emit the correct MMU index information for loads and stores from
A64 code, rather than hardwiring it to "always kernel mode",
by storing the exception level in the TB flags, and make
cpu_mmu_index() return the right answer when the CPU is in
AArch64 mode.
Peter Maydell [Wed, 26 Feb 2014 17:20:05 +0000 (17:20 +0000)]
target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI
Define a dummy version of the AArch64 OSLAR_EL1 system register
which just ignores writes. Linux will always write to this (it
is the OS lock used for debugging), but we don't support debug.
Peter Maydell [Wed, 26 Feb 2014 17:20:05 +0000 (17:20 +0000)]
target-arm: Implement AArch64 dummy breakpoint and watchpoint registers
In AArch64 the breakpoint and watchpoint registers are mandatory, so the
kernel always accesses them on bootup. Implement dummy versions, which
read as written but have no actual effect.
Peter Maydell [Wed, 26 Feb 2014 17:20:05 +0000 (17:20 +0000)]
target-arm: Implement AArch64 ID and feature registers
Implement the AArch64-specific ID and feature registers. Although
many of these are currently not used by the architecture (and so
always zero for all implementations), we define the full set of
fields in the ARMCPU struct for symmetry.
Peter Maydell [Wed, 26 Feb 2014 17:20:04 +0000 (17:20 +0000)]
target-arm: Implement AArch64 TTBR*
Implement the AArch64 TTBR* registers. For v7 these were already 64 bits
to handle LPAE, but implemented as two separate uint32_t fields.
Combine them into a single uint64_t which can be used for all purposes.
Since this requires touching every use, take the opportunity to rename
the field to the architectural name.
Peter Maydell [Wed, 26 Feb 2014 17:20:04 +0000 (17:20 +0000)]
target-arm: Implement AArch64 TCR_EL1
Implement the AArch64 TCR_EL1, which is the 64 bit view of
the AArch32 TTBCR. (The uses of the bits in the register are
completely different, but in any given situation the CPU will
always interpret them one way or the other. In fact for QEMU EL1
is always 64 bit, but we share the state field because this
is the correct mapping to permit a future implementation of EL2.)
We also make the AArch64 view the 'master' as far as migration
and reset is concerned.
Implement the AArch64 memory attribute registers. Since QEMU doesn't
model caches it does not need to care about memory attributes at all,
and we can simply make these read-as-written.
We did not previously implement the AArch32 versions of the MAIR
registers, which went unnoticed because of the overbroad TLB_LOCKDOWN
reginfo definition; provide them now to keep the 64<->32 register
relationship clear.
We already provided AMAIR registers for 32 bit as simple RAZ/WI;
extend that to provide a 64 bit RAZ/WI AMAIR_EL1.
Implement all the AArch64 cache invalidate and clean ops
(which are all NOPs since QEMU doesn't emulate the cache).
The only remaining unimplemented cache op is DC ZVA.
Peter Maydell [Wed, 26 Feb 2014 17:20:02 +0000 (17:20 +0000)]
target-arm: Implement AArch64 MIDR_EL1
Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).
Peter Maydell [Wed, 26 Feb 2014 17:20:01 +0000 (17:20 +0000)]
target-arm: A64: Make cache ID registers visible to AArch64
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)
visible to AArch64. These are mostly simple 64-bit extensions of the
existing 32 bit system registers and so can share reginfo definitions.
CTR needs to have a split definition, but we can clean up the
temporary user-mode implementation in favour of using the CPU-specified
reset value, and implement the system-mode-required semantics of
restricting its EL0 accessibility if SCTLR.UCT is not set.
Peter Maydell [Wed, 26 Feb 2014 17:20:01 +0000 (17:20 +0000)]
target-arm: Fix raw read and write functions on AArch64 registers
The raw read and write functions were using the ARM_CP_64BIT flag in
ri->type to determine whether to treat the register's state field as
uint32_t or uint64_t; however AArch64 register info structs don't use
that flag. Abstract out the "how big is the field?" test into a
function and fix it to work for AArch64 registers. For this to work
we must ensure that the reginfo structs put into the hashtable have
the correct state field for their use, not the placeholder STATE_BOTH.
Christoffer Dall [Wed, 26 Feb 2014 17:20:01 +0000 (17:20 +0000)]
hw: arm_gic_kvm: Add KVM VGIC save/restore logic
Save and restore the ARM KVM VGIC state from the kernel. We rely on
QEMU to marshal the GICState data structure and therefore simply
synchronize the kernel state with the QEMU emulated state in both
directions.
We take some care on the restore path to check the VGIC has been
configured with enough IRQs and CPU interfaces that we can properly
restore the state, and for separate set/clear registers we first fully
clear the registers and then set the required bits.
Christoffer Dall [Wed, 26 Feb 2014 17:20:00 +0000 (17:20 +0000)]
arm: vgic device control api support
Support creating the ARM vgic device through the device control API and
setting the base address for the distributor and cpu interfaces in KVM
VMs using this API.
Because the older KVM_CREATE_IRQCHIP interface needs the irq chip to be
created prior to creating the VCPUs, we first test if we can use the
device control API in kvm_arch_irqchip_create (using the test flag from
the device control API). If we cannot, it means we have to fall back to
KVM_CREATE_IRQCHIP and use the older ioctl at this point in time. If
however, we can use the device control API, we don't do anything and
wait until the arm_gic_kvm driver initializes and let that use the
device control API.
Christoffer Dall [Wed, 26 Feb 2014 17:19:59 +0000 (17:19 +0000)]
hw/intc/arm_gic: Fix GIC_SET_LEVEL
The GIC_SET_LEVEL macro unfortunately overwrote the entire level
bitmask instead of just or'ing on the necessary bits, causing active
level PPIs on a core to clear PPIs on other cores.
In ARMv5 level 2 page table descriptors, each 4K or 64K page is split into
four subpages, each of which can have different access permission settings,
which are specified by four two-bit fields in the l2 descriptor. A
long-standing cut-and-paste error meant we were using the wrong bits in
the virtual address to select the access-permission field for 4K pages.
The error has presumably not been noticed before because most guests don't
make use of the ability to set the access permissions differently for
each 1K subpage: if the guest gives the whole page the same access
permissions it doesn't matter which of the 4 AP fields we select.
(The whole issue is irrelevant for ARMv7 CPUs anyway because subpages
aren't supported there.)
The ethernet device in the musicpal only has two tx queues,
but we modelled it with four CTDP registers, presumably a
cut and paste from the rx queue registers. Since the tx_queue[]
array is only 2 entries long this allowed a guest to overrun
this buffer. Remove the nonexistent registers.
Peter Maydell [Wed, 26 Feb 2014 17:19:58 +0000 (17:19 +0000)]
hw/intc/exynos4210_combiner: Don't overrun output_irq array in init
The Exynos4210 combiner has IIC_NIRQ inputs and IIC_NGRP outputs;
use the correct constant in the loop initializing our output
sysbus IRQs so that we don't overrun the output_irq[] array.
Peter Maydell [Wed, 26 Feb 2014 17:19:58 +0000 (17:19 +0000)]
hw/timer/arm_timer: Avoid array overrun for bad addresses
The integrator's timer read/write functions log an error for
bad addresses in guest accesses, but were falling through and
using an out of bounds array index rather than returning early.
Fix this.
Add a cast to avoid an unintended sign extension that
would mean we returned 0xffffffff in the high 32 bits
for an IA0 read if bit 31 in the MAC address was 1.
(This is harmless since we'll only be doing 4 byte
reads, but it could be confusing, so best avoided.)
Peter Maydell [Wed, 26 Feb 2014 17:19:57 +0000 (17:19 +0000)]
hw/misc/arm_sysctl: Fix bad boundary check on mb clock accesses
Fix incorrect use of sizeof() rather than ARRAY_SIZE() to guard
accesses into the mb_clock[] array, which was allowing a malicious
guest to overwrite the end of the array.
Paolo Bonzini [Tue, 25 Feb 2014 16:36:55 +0000 (17:36 +0100)]
modules: do not include gmodule-2.0 in static builds
gmodule-2.0's pkg-config files include -Wl,--export-dynamic, which breaks
static builds. It is a glib bug, but we need to support --static builds for
the linux-user targets, and in the end all that is needed to fix this is:
* outlaw --enable-modules --static, which makes little sense anyway
* only include gmodule-2.0's cflags and ldflags if --enable-modules is
specified on the command line.
Stefan Hajnoczi [Thu, 20 Feb 2014 11:14:07 +0000 (12:14 +0100)]
net: remove implicit peer from offload API
The virtio_net offload APIs are used on the NIC's peer (i.e. the tap
device). The API was defined to implicitly use nc->peer, saving the
caller the trouble.
This wasn't ideal because:
1. There are callers who have the peer but not the NIC. Currently they
are forced to bypass the API and access peer->info->... directly.
2. The rest of the net.h API uses nc, not nc->peer, so it is
inconsistent.
Michael R. Hines [Wed, 18 Dec 2013 20:52:01 +0000 (04:52 +0800)]
rdma: rename 'x-rdma' => 'rdma'
As far as we can tell, all known bugs have been fixed:
1. Parallel migrations are working
2. IPv6 migration is working
3. virt-test is working
I'm not comfortable sending the revised libvirt patch
until this is accepted or review suggestions are addressed,
(including pin-all support. It does not make sense to
remove experimental for one thing and not the other. That's
too many trips through the libvirt community).
Push zero'd pages into the XBZRLE cache
A page that was cached by XBZRLE, zero'd and then XBZRLE'd again
was being compared against a stale cache value
Don't use 'qemu_put_buffer_async' to put pages from the XBZRLE cache
Since the cache might change before the data hits the wire
Fix comparison of vmstate_info_int32_le so that it succeeds if loaded
value is (l)ess than or (e)qual
When the comparison succeeds, assign the value loaded
This is a change in behaviour but I think the original intent, since
the idea is to check if the version/size of the thing you're loading is
less than some limit, but you might well want to do something based on
the actual version/size in the file
Juan Quintela [Tue, 11 Feb 2014 21:56:00 +0000 (22:56 +0100)]
qemu_file: use fwrite() correctly
fwrite() returns the number of items written. But when there is one
error, it can return a short write.
In the particular bug that I was tracking, I did a migration to a
read-only filesystem. And it was able to finish the migration
correctly. fwrite() never returned a negative error code, nor zero,
always 4096. (migration writes chunks of about 14000 bytes). And it
was able to "complete" the migration with success (yes, reading the
file was a bit more difficult).
To add insult to injury, if your amount of memory was big enough (12GB
on my case), it overwrote some important structure, and from them,
malloc failed. This check makes the problem go away.
Peter Maydell [Tue, 25 Feb 2014 12:30:01 +0000 (12:30 +0000)]
Merge remote-tracking branch 'remotes/mdroth/qga-pull-2014-02-24' into staging
* remotes/mdroth/qga-pull-2014-02-24:
qemu-ga: isa-serial support on Windows
qga: Fix memory allocation pasto
qga: Don't require 'time' argument in guest-set-time command
qga: vss-win32: Fix interference with snapshot deletion by other VSS request
qga: vss-win32: Fix interference with snapshot creation by other VSS requesters
qga: vss-win32: Use NULL as an invalid pointer for OpenEvent and CreateEvent
Peter Maydell [Tue, 25 Feb 2014 11:54:40 +0000 (11:54 +0000)]
Merge remote-tracking branch 'remotes/xtensa/tags/20140224-xtensa' into staging
Xtensa fixes and improvements queue 2014-02-24:
- add support for ML605 and KC705 FPGA boards;
- flush opencores_eth queue when new RX descriptor is available;
- add basic checks to cache opcodes;
- make core configuration available to tests;
- implement HW config ID special registers.
# gpg: Signature made Mon 24 Feb 2014 00:52:42 GMT using RSA key ID F83FA044
# gpg: Good signature from "Max Filippov <[email protected]>"
# gpg: aka "Max Filippov <[email protected]>"
* remotes/xtensa/tags/20140224-xtensa:
target-xtensa: provide HW confg ID registers
target-xtensa: refactor standard core configuration
target-xtensa: add basic tests for cache opcodes
target-xtensa: allow using core configuration in tests
target-xtensa: add overridable test_init macro
target-xtensa: add basic checks to icache opcodes
target-xtensa: add basic checks to dcache opcodes
target-xtensa: add RRRI4 opcode format fields
opencores_eth: flush queue whenever can_receive can go from false to true
hw/xtensa: add support for ML605 and KC705 FPGA board
This patch fixes configure so that the netmap backend is not compiled in if the
host doesn't support an API version >= 11. A version upper bound (15) has been
added so that the netmap API can be extended with some minor features without
requiring QEMU code modifications.
Moreover, some changes have been done to net/netmap.c in order to reflect the
current netmap API/ABI (11).
The NETMAP_WITH_LIBS macro makes possible to include some utilities (e.g.
netmap ring macros, D(), RD() and other high level functions) through the netmap
headers. In this way we get rid of the D and RD macro definitions in the QEMU
code, and we open the way for further code simplifications that will be
introduced by future patches.
Whit this patch, the netmap backend supports TSO/UFO/CSUM
offloadings, and accepts the virtio-net header, similarly to what
happens with TAP. The offloading callbacks in the NetClientInfo
interface have been implemented.
With this patch, virtio-net and vmxnet3 frontends make
use of the qemu_peer_* API for backend offloadings manipulations,
instead of calling TAP-specific functions directly.
We also remove the existing checks which prevent those frontends
from using offloadings with backends different from TAP (e.g. netmap).
The tap_has_vnet_hdr() and tap_has_vnet_hdr_len() functions used
to return int, even though they only return true/false values.
This patch changes the prototypes to return bool.
Max Filippov [Mon, 3 Feb 2014 04:20:02 +0000 (08:20 +0400)]
opencores_eth: flush queue whenever can_receive can go from false to true
The following registers control whether MAC can receive frames:
- MODER.RXEN bit that enables/disables receiver;
- TX_BD_NUM register that specifies number of RX descriptors.
Notify QEMU networking core when the MAC is ready to receive frames.
Discard frame and raise BUSY interrupt when the frame arrives but the
current RX descriptor is not empty.
Peter Maydell [Tue, 25 Feb 2014 10:50:11 +0000 (10:50 +0000)]
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Block patches
# gpg: Signature made Fri 21 Feb 2014 21:42:24 GMT using RSA key ID C88F2FD6
# gpg: Good signature from "Kevin Wolf <[email protected]>"
* remotes/kevin/tags/for-upstream: (54 commits)
iotests: Mixed quorum child device specifications
quorum: Simplify quorum_open()
quorum: Add unit test.
quorum: Add quorum_open() and quorum_close().
quorum: Implement recursive .bdrv_recurse_is_first_non_filter in quorum.
quorum: Add quorum_co_flush().
quorum: Add quorum_invalidate_cache().
quorum: Add quorum_getlength().
quorum: Add quorum mechanism.
quorum: Add quorum_aio_readv.
blkverify: Extract qemu_iovec_clone() and qemu_iovec_compare() from blkverify.
quorum: Add quorum_aio_writev and its dependencies.
quorum: Create BDRVQuorumState and BlkDriver and do init.
quorum: Create quorum.c, add QuorumChildRequest and QuorumAIOCB.
check-qdict: Test termination of qdict_array_split()
check-qdict: Adjust test for qdict_array_split()
qdict: Extract non-QDicts in qdict_array_split()
qemu-config: Sections must consist of keys
qemu-iotests: Check qemu-img command line parsing
qemu-img: Allow -o help with incomplete argument list
...
Peter Maydell [Mon, 24 Feb 2014 15:37:59 +0000 (15:37 +0000)]
Merge remote-tracking branch 'remotes/bonzini/configure' into staging
* remotes/bonzini/configure:
build: softmmu targets do not have a "main.o" file
configure: Disable libtool if -fPIE does not work with it (bug #1257099)
block: convert block drivers linked with libs to modules
Makefile: introduce common-obj-m and block-obj-m for DSO
Makefile: install modules with "make install"
module: implement module loading
rules.mak: introduce DSO rules
darwin: do not use -mdynamic-no-pic
block: use per-object cflags and libs
rules.mak: allow per object cflags and libs
rules.mak: fix $(obj) to a real relative path
util: Split out exec_dir from os_find_datadir
Peter Maydell [Thu, 20 Feb 2014 15:10:16 +0000 (15:10 +0000)]
configure: check that C++ compiler actually works
Check that the C++ compiler works with the C compiler; if it
does not, then don't pass CXX to the build process. This
fixes a regression where QEMU was no longer building if the
build environment didn't have a C++ compiler (introduced
in commit 3144f78b, which incorrectly assumed that rules.mak
would only see a non-empty $(CXX) if configure had actually
found a working C++ compiler).
Max Filippov [Sat, 15 Feb 2014 16:58:47 +0000 (20:58 +0400)]
target-xtensa: refactor standard core configuration
Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h
Max Filippov [Fri, 7 Feb 2014 11:57:22 +0000 (15:57 +0400)]
target-xtensa: add basic checks to icache opcodes
Check privilege level for privileged instructions (IHU, III, IIU and IPFL
are privileged), memory accessibility for instructions that reference memory
(IH* and IPFL) and windowed register validity for all instruction cache
instructions.
Max Filippov [Fri, 7 Feb 2014 11:57:22 +0000 (15:57 +0400)]
target-xtensa: add basic checks to dcache opcodes
Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,
DIWBI, DPFL are privileged), memory accessibility for instructions that
reference memory (all DH* and DPFL) and windowed register validity for all
data cache instructions.
Max Filippov [Mon, 3 Feb 2014 03:57:55 +0000 (07:57 +0400)]
opencores_eth: flush queue whenever can_receive can go from false to true
The following registers control whether MAC can receive frames:
- MODER.RXEN bit that enables/disables receiver;
- TX_BD_NUM register that specifies number of RX descriptors.
Notify QEMU networking core when the MAC is ready to receive frames.
Discard frame and raise BUSY interrupt when the frame arrives but the
current RX descriptor is not empty.
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