Paolo Bonzini [Fri, 28 Feb 2020 15:35:56 +0000 (15:35 +0000)]
qemu-doc: move qemu-tech.texi into main section
The only remaining content in qemu-tech.texi is a few paragraphs
about managed start up options. Move them in the main section
about full system emulation.
Peter Maydell [Fri, 28 Feb 2020 15:35:55 +0000 (15:35 +0000)]
qemu-doc: Remove the "CPU emulation" part of the "Implementation notes"
The "CPU emulation" part of the "Implementation notes" in
qemu-tech.texi looks like it is documenting what features of various
CPUs we do or don't emulate. However:
* it covers only six of our 21 guest architectures
* the last time anybody updated it for actual content was in
2011/2012 for Xtensa; the content for the other five
architectures is even older, being from 2008 or before!
What we have is out of date, misleading and incomplete.
Just delete this part of the document rather than trying to
convert it to rST.
(It would be nice eventually to have documentation of the
scope and limitations of our emulation; but we will want to
separate out the generic "system emulation" information from
the parts that are specific to linux-user anyway, as they will
be in different manuals.)
Paolo Bonzini [Fri, 28 Feb 2020 15:35:52 +0000 (15:35 +0000)]
qemu-doc: extract common system emulator documentation from the PC section
Move the section on PC peripherals together with other targets.
While some x86-specific information remains in the main system
emulation chapter, it can be tackled more easily a section at a
time.
Paolo Bonzini [Fri, 28 Feb 2020 15:35:51 +0000 (15:35 +0000)]
qemu-doc: split qemu-doc.texi in multiple files
In order to facilitate the reorganization of qemu-doc.texi content,
as well as the conversion to rST/Sphinx, split it in multiple .texi
files that are included from docs/system.
The "other devices" section is renamed to ivshmem and placed last.
This enables splitting the huge qemu-doc.texi file and keeping parallel
Texinfo and rST versions of the documentation. texi2pod is not going to
live much longer and hardly anyone cares about its upstream status,
so the temporary fork should be acceptable.
Paolo Bonzini [Fri, 28 Feb 2020 15:35:47 +0000 (15:35 +0000)]
qemu-doc: convert user-mode emulation to a separate Sphinx manual
The final addition to the set of QEMU manuals is the user-mode emulation
manual, which right now is included in qemu-doc.texi. Extract it and
convert it to rST, so that qemu-doc.texi covers only full system emulation.
Palmer Dabbelt [Thu, 5 Mar 2020 16:46:20 +0000 (08:46 -0800)]
RISC-V: Add a missing "," in riscv_excp_names
This would almost certainly cause the exception names to be reported
incorrectly. Coverity found the issue (CID 1420223). As per Peter's
suggestion, I've also added a comma at the end of the list to avoid the issue
reappearing in the future.
Fixes: ab67a1d07a ("target/riscv: Add support for the new execption numbers") Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
Peter Maydell [Thu, 5 Mar 2020 19:39:47 +0000 (19:39 +0000)]
Merge remote-tracking branch 'remotes/stefanberger/tags/pull-tpm-2020-03-04-2' into staging
Merge tpm 2020/03/04 v2
# gpg: Signature made Thu 05 Mar 2020 17:21:05 GMT
# gpg: using RSA key B818B9CADF9089C2D5CEC66B75AD65802A0B4211
# gpg: Good signature from "Stefan Berger <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211
* remotes/stefanberger/tags/pull-tpm-2020-03-04-2:
test: tpm-tis: Add Sysbus TPM-TIS device test
test: tpm-tis: Get prepared to share tests between ISA and sysbus devices
test: tpm: pass optional machine options to swtpm test functions
docs/specs/tpm: Document TPM_TIS sysbus device for ARM
hw/arm/virt: vTPM support
tpm: Add the SysBus TPM TIS device
tpm: Separate TPM_TIS and TPM_TIS_ISA configs
tpm: Separate tpm_tis common functions from isa code
tpm: Use TPMState as a common struct
tpm: rename TPM_TIS into TPM_TIS_ISA
Eric Auger [Thu, 5 Mar 2020 16:51:49 +0000 (17:51 +0100)]
test: tpm-tis: Add Sysbus TPM-TIS device test
The tests themselves are the same as the ISA device ones.
Only the main() changes as the "tpm-tis-device" device gets
instantiated. Also the base address of the device is not
0xFED40000 anymore but matches the base address of the
ARM virt platform bus.
Eric Auger [Thu, 5 Mar 2020 16:51:48 +0000 (17:51 +0100)]
test: tpm-tis: Get prepared to share tests between ISA and sysbus devices
ISA and sysbus TPM-TIS devices will share their tests. Only
the main() will change (instantiation option is different).
Also the base address of the TPM-TIS device is going to be
different. on x86 it is located at 0xFED40000 while on ARM
it can be located at any location, discovered through the
device tree description.
So we put shared test functions in a new object module.
Each test needs to set tpm_tis_base_addr global variable.
Also take benefit of this move to fix "block comments using
a leading */ on a separate line" checkpatch warnings.
Eric Auger [Thu, 5 Mar 2020 16:51:47 +0000 (17:51 +0100)]
test: tpm: pass optional machine options to swtpm test functions
We plan to use swtpm test functions on ARM for testing the
sysbus TPM-TIS device. However on ARM there is no default machine
type. So we need to explictly pass some machine options on startup.
Let's allow this by adding a new parameter to both swtpm test
functions and update all call sites.
Eric Auger [Thu, 5 Mar 2020 16:51:41 +0000 (17:51 +0100)]
tpm: Use TPMState as a common struct
As we plan to introduce a SysBus TPM TIS device, let's
make the TPMState a common struct usable by both the
ISADevice and the SysBusDevice. TPMStateISA embeds the
struct and inherits from the ISADevice.
The prototype of functions bound to be used by both
the ISA and SysBus devices is changed to take TPMState
handle.
A bunch of structs also are renamed to be specialized
for the ISA device. Besides those transformations, no
functional change is expected.
Peter Maydell [Thu, 5 Mar 2020 16:47:37 +0000 (16:47 +0000)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200305' into staging
* versal: Implement ADMA
* Implement (trivially) ARMv8.2-TTCNP
* hw/arm/smmu-common: a fix to smmu_find_smmu_pcibus
* Remove unnecessary endianness-handling on some boards
* Avoid minor memory leaks from timer_new in some devices
* Honour more of the HCR_EL2 trap bits
* Complain rather than ignoring bad command line options for cubieboard
* Honour TBI for DC ZVA and exception return
* remotes/pmaydell/tags/pull-target-arm-20200305: (37 commits)
target/arm: Clean address for DC ZVA
target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva
target/arm: Move helper_dc_zva to helper-a64.c
target/arm: Apply TBI to ESR_ELx in helper_exception_return
target/arm: Introduce core_to_aa64_mmu_idx
target/arm: Optimize cpu_mmu_index
target/arm: Replicate TBI/TBID bits for single range regimes
hw/arm/cubieboard: report error when using unsupported -bios argument
hw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiB
hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8
hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition
tests/tcg/aarch64: Add newline in pauth-1 printf
target/arm: Honor the HCR_EL2.TTLB bit
target/arm: Honor the HCR_EL2.TPU bit
target/arm: Honor the HCR_EL2.TPCP bit
target/arm: Honor the HCR_EL2.TACR bit
target/arm: Honor the HCR_EL2.TSW bit
target/arm: Honor the HCR_EL2.{TVM,TRVM} bits
target/arm: Improve masking in arm_hcr_el2_eff
target/arm: Remove EL2 and EL3 setup from user-only
...
We now cache the core mmu_idx in env->hflags. Rather than recompute
from scratch, extract the field. All of the uses of cpu_mmu_index
within target/arm are within helpers, and env->hflags is always stable
within a translation block from whence helpers are called.
Niek Linnenbank [Thu, 5 Mar 2020 16:09:19 +0000 (16:09 +0000)]
hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8
The Cubieboard has an ARM Cortex-A8. Instead of simply ignoring a
bogus -cpu option provided by the user, give them an error message so
they know their command line is wrong.
Niek Linnenbank [Thu, 5 Mar 2020 16:09:19 +0000 (16:09 +0000)]
hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition
The Cubieboard is a singleboard computer with an Allwinner A10 System-on-Chip [1].
As documented in the Allwinner A10 User Manual V1.5 [2], the SoC has an ARM
Cortex-A8 processor. Currently the Cubieboard machine definition specifies the
ARM Cortex-A9 in its description and as the default CPU.
This patch corrects the Cubieboard machine definition to use the ARM Cortex-A8.
The only user-visible effect is that our textual description of the
machine was wrong, because hw/arm/allwinner-a10.c always creates a
Cortex-A8 CPU regardless of the default value in the MachineClass struct.
This bit traps EL1 access to cache maintenance insns that operate
to the point of unification. There are no longer any references to
plain aa64_cacheop_access, so remove it.
target/arm: Disable has_el2 and has_el3 for user-only
In arm_cpu_reset, we configure many system registers so that user-only
behaves as it should with a minimum of ifdefs. However, we do not set
all of the system registers as required for a cpu with EL2 and EL3.
Disabling EL2 and EL3 mean that we will not look at those registers,
which means that we don't have to worry about configuring them.
Don't merely start with v8.0, handle v7VE as well. Ensure that writes
from aarch32 mode do not change bits in the other half of the register.
Protect reads of aa64 id registers with ARM_FEATURE_AARCH64.
The smmu_find_smmu_pcibus() function was introduced (in commit cac994ef43b) in a code format that could return an incorrect
pointer, which was then fixed by the previous commit.
We could have avoided this by writing the if() statement
differently. Do it now, in case this function is re-used.
The code is easier to review (harder to miss bugs).
Peter Maydell [Thu, 5 Mar 2020 16:09:14 +0000 (16:09 +0000)]
target/arm: Implement (trivially) ARMv8.2-TTCNP
The ARMv8.2-TTCNP extension allows an implementation to optimize by
sharing TLB entries between multiple cores, provided that software
declares that it's ready to deal with this by setting a CnP bit in
the TTBRn_ELx. It is mandatory from ARMv8.2 onward.
For QEMU's TLB implementation, sharing TLB entries between different
cores would not really benefit us and would be a lot of work to
implement. So we implement this extension in the "trivial" manner:
we allow the guest to set and read back the CnP bit, but don't change
our behaviour (this is an architecturally valid implementation
choice).
The only code path which looks at the TTBRn_ELx values for the
long-descriptor format where the CnP bit is defined is already doing
enough masking to not get confused when the CnP bit at the bottom of
the register is set, so we can simply add a comment noting why we're
relying on that mask.
* remotes/armbru/tags/pull-qapi-2020-03-05:
qapi: Brush off some (py)lint
qapi: Use super() now we have Python 3
qapi: Drop conditionals for Python 2
qapi: Inheriting from object is pointless with Python 3, drop
Peter Maydell [Thu, 5 Mar 2020 12:13:51 +0000 (12:13 +0000)]
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-040320-1' into staging
Testing updates
- some clean-ups for tests/vm
- enable tools build for MacOSX
- bump avocado to a newer version
- bump travis env for avocado
# gpg: Signature made Wed 04 Mar 2020 10:00:19 GMT
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <[email protected]>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* remotes/stsquad/tags/pull-testing-040320-1:
travis.yml: install python3 numpy and opencv libraries
tests/acceptance: bump avocado requirements to 76.0
configure: detect and report genisoimage
travis: enable tools build on OS X
tests/vm: Added gen_cloud_init_iso() to basevm.py
tests/vm: give wait_ssh() option to wait for root
tests/vm: increased max timeout for vm boot.
tests/vm: Debug mode shows ssh output.
tests/vm: use $(PYTHON) consistently
Robert Foley [Tue, 3 Mar 2020 15:06:17 +0000 (15:06 +0000)]
tests/vm: give wait_ssh() option to wait for root
Allow wait_ssh to wait for root user to be ready.
This solves the issue where we perform a wait_ssh()
successfully, but the root user is not yet ready
to be logged in.
Misono Tomohiro [Thu, 27 Feb 2020 05:59:27 +0000 (14:59 +0900)]
virtiofsd: Fix xattr operations
Current virtiofsd has problems about xattr operations and
they does not work properly for directory/symlink/special file.
The fundamental cause is that virtiofsd uses openat() + f...xattr()
systemcalls for xattr operation but we should not open symlink/special
file in the daemon. Therefore the function is restricted.
Fix this problem by:
1. during setup of each thread, call unshare(CLONE_FS)
2. in xattr operations (i.e. lo_getxattr), if inode is not a regular
file or directory, use fchdir(proc_loot_fd) + ...xattr() +
fchdir(root.fd) instead of openat() + f...xattr()
(Note: for a regular file/directory openat() + f...xattr()
is still used for performance reason)
With this patch, xfstests generic/062 passes on virtiofs.
This fix is suggested by Miklos Szeredi and Stefan Hajnoczi.
The original discussion can be found here:
https://www.redhat.com/archives/virtio-fs/2019-October/msg00046.html
This is a cleanup patch to simplify the following xattr fix and
there is no functional changes.
- Move memory allocation to head of the function
- Unify fgetxattr/flistxattr call for both size == 0 and
size != 0 case
- Remove redundant lo_inode_put call in error path
(Note: second call is ignored now since @inode is already NULL)
Peter Maydell [Tue, 3 Mar 2020 12:03:59 +0000 (12:03 +0000)]
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging
# gpg: Signature made Tue 03 Mar 2020 10:06:06 GMT
# gpg: using RSA key EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <[email protected]>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211
* remotes/jasowang/tags/net-pull-request: (23 commits)
l2tpv3: fix RFC number typo in qemu-options.hx
colo: Update Documentation for continuous replication
net/filter.c: Add Options to insert filters anywhere in the filter list
tests/test-replication.c: Add test for for secondary node continuing replication
block/replication.c: Ignore requests after failover
hw: net: cadence_gem: Fix build errors in DB_PRINT()
NetRxPkt: fix hash calculation of IPV6 TCP
NetRxPkt: Introduce support for additional hash types
e1000e: Avoid hw_error if legacy mode used
dp8393x: Don't stop reception upon RBE interrupt assertion
dp8393x: Don't reset Silicon Revision register
dp8393x: Always update RRA pointers and sequence numbers
dp8393x: Clear descriptor in_use field to release packet
dp8393x: Pad frames to word or long word boundary
dp8393x: Use long-word-aligned RRA pointers in 32-bit mode
dp8393x: Don't clobber packet checksum
dp8393x: Implement packet size limit and RBAE interrupt
dp8393x: Clear RRRA command register bit only when appropriate
dp8393x: Update LLFA and CRDA registers from rx descriptor
dp8393x: Have dp8393x_receive() return the packet size
...
Peter Maydell [Tue, 3 Mar 2020 11:06:39 +0000 (11:06 +0000)]
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' into staging
RISC-V Patches for the 5.0 Soft Freeze, Part 3
This pull request is almost entirely an implementation of the draft hypervisor
extension. This extension is still in draft and is expected to have
incompatible changes before being frozen, but we've had good luck managing
other RISC-V draft extensions in QEMU so far.
Additionally, there's a fix to PCI addressing and some improvements to the
M-mode timer.
This boots linux and passes make check for me.
# gpg: Signature made Tue 03 Mar 2020 00:23:20 GMT
# gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg: issuer "[email protected]"
# gpg: Good signature from "Palmer Dabbelt <[email protected]>" [unknown]
# gpg: aka "Palmer Dabbelt <[email protected]>" [unknown]
# gpg: aka "Palmer Dabbelt <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41
# Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889
* remotes/palmer/tags/riscv-for-master-5.0-sf3: (38 commits)
hw/riscv: Provide rdtime callback for TCG in CLINT emulation
target/riscv: Emulate TIME CSRs for privileged mode
riscv: virt: Allow PCI address 0
target/riscv: Allow enabling the Hypervisor extension
target/riscv: Add the MSTATUS_MPV_ISSET helper macro
target/riscv: Add support for the 32-bit MSTATUSH CSR
target/riscv: Set htval and mtval2 on execptions
target/riscv: Raise the new execptions when 2nd stage translation fails
target/riscv: Implement second stage MMU
target/riscv: Allow specifying MMU stage
target/riscv: Respect MPRV and SPRV for floating point ops
target/riscv: Mark both sstatus and msstatus_hs as dirty
target/riscv: Disable guest FP support based on virtual status
target/riscv: Only set TB flags with FP status if enabled
target/riscv: Remove the hret instruction
target/riscv: Add hfence instructions
target/riscv: Add Hypervisor trap return support
target/riscv: Add hypvervisor trap support
target/riscv: Generate illegal instruction on WFI when V=1
target/ricsv: Flush the TLB on virtulisation mode changes
...
Lukas Straub [Thu, 24 Oct 2019 14:25:48 +0000 (16:25 +0200)]
net/filter.c: Add Options to insert filters anywhere in the filter list
To switch the Secondary to Primary, we need to insert new filters
before the filter-rewriter.
Add the options insert= and position= to be able to insert filters
anywhere in the filter list.
position should be "head" or "tail" to insert at the head or
tail of the filter list or it should be "id=<id>" to specify
the id of another filter.
insert should be either "before" or "behind" to specify where to
insert the new filter relative to the one specified with position.
Lukas Straub [Thu, 24 Oct 2019 14:25:35 +0000 (16:25 +0200)]
block/replication.c: Ignore requests after failover
After failover the Secondary side of replication shouldn't change state, because
it now functions as our primary disk.
In replication_start, replication_do_checkpoint, replication_stop, ignore
the request if current state is BLOCK_REPLICATION_DONE (sucessful failover) or
BLOCK_REPLICATION_FAILOVER (failover in progres i.e. currently merging active
and hidden images into the base image).
Yuri Benditovich [Mon, 27 Jan 2020 11:54:05 +0000 (13:54 +0200)]
NetRxPkt: fix hash calculation of IPV6 TCP
When requested to calculate the hash for TCPV6 packet,
ignore overrides of source and destination addresses
in in extension headers.
Use these overrides when new hash type NetPktRssIpV6TcpEx
requested.
Use this type in e1000e hash calculation for IPv6 TCP, which
should take in account overrides of the addresses.
Yuri Benditovich [Mon, 27 Jan 2020 16:03:12 +0000 (18:03 +0200)]
e1000e: Avoid hw_error if legacy mode used
https://bugzilla.redhat.com/show_bug.cgi?id=1787142
The emulation issues hw_error if PSRCTL register
is written, for example, with zero value.
Such configuration does not present any problem when
DTYP bits of RCTL register define legacy format of
transfer descriptors. Current commit discards check
for BSIZE0 and BSIZE1 when legacy mode used.
Finn Thain [Wed, 29 Jan 2020 09:27:49 +0000 (20:27 +1100)]
dp8393x: Don't stop reception upon RBE interrupt assertion
Section 3.4.7 of the datasheet explains that,
The RBE bit in the Interrupt Status register is set when the
SONIC finishes using the second to last receive buffer and reads
the last RRA descriptor. Actually, the SONIC is not truly out of
resources, but gives the system an early warning of an impending
out of resources condition.
RBE does not mean actual receive buffer exhaustion, and reception should
not be stopped. This is important because Linux will not check and clear
the RBE interrupt until it receives another packet. But that won't
happen if can_receive returns false. This bug causes the SONIC to become
deaf (until reset).
Fix this with a new flag to indicate actual receive buffer exhaustion.
Finn Thain [Wed, 29 Jan 2020 09:27:49 +0000 (20:27 +1100)]
dp8393x: Don't reset Silicon Revision register
The jazzsonic driver in Linux uses the Silicon Revision register value
to probe the chip. The driver fails unless the SR register contains 4.
Unfortunately, reading this register in QEMU usually returns 0 because
the s->regs[] array gets wiped after a software reset.
Finn Thain [Wed, 29 Jan 2020 09:27:49 +0000 (20:27 +1100)]
dp8393x: Pad frames to word or long word boundary
The existing code has a bug where the Remaining Buffer Word Count (RBWC)
is calculated with a truncating division, which gives the wrong result
for odd-sized packets.
Section 1.4.1 of the datasheet says,
Once the end of the packet has been reached, the serializer will
fill out the last word (16-bit mode) or long word (32-bit mode)
if the last byte did not end on a word or long word boundary
respectively. The fill byte will be 0FFh.
Implement buffer padding so that buffer limits are correctly enforced.
Finn Thain [Wed, 29 Jan 2020 09:27:49 +0000 (20:27 +1100)]
dp8393x: Use long-word-aligned RRA pointers in 32-bit mode
Section 3.4.1 of the datasheet says,
The alignment of the RRA is confined to either word or long word
boundaries, depending upon the data width mode. In 16-bit mode,
the RRA must be aligned to a word boundary (A0 is always zero)
and in 32-bit mode, the RRA is aligned to a long word boundary
(A0 and A1 are always zero).
This constraint has been implemented for 16-bit mode; implement it
for 32-bit mode too.
Finn Thain [Wed, 29 Jan 2020 09:27:49 +0000 (20:27 +1100)]
dp8393x: Don't clobber packet checksum
A received packet consumes pkt_size bytes in the buffer and the frame
checksum that's appended to it consumes another 4 bytes. The Receive
Buffer Address register takes the former quantity into account but
not the latter. So the next packet written to the buffer overwrites
the frame checksum. Fix this.
Finn Thain [Wed, 29 Jan 2020 09:27:49 +0000 (20:27 +1100)]
dp8393x: Implement packet size limit and RBAE interrupt
Add a bounds check to prevent a large packet from causing a buffer
overflow. This is defensive programming -- I haven't actually tried
sending an oversized packet or a jumbo ethernet frame.
The SONIC handles packets that are too big for the buffer by raising
the RBAE interrupt and dropping them. Linux uses that interrupt to
count dropped packets.
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