}
}
+static void versal_create_admas(Versal *s, qemu_irq *pic)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) {
+ char *name = g_strdup_printf("adma%d", i);
+ DeviceState *dev;
+ MemoryRegion *mr;
+
+ dev = qdev_create(NULL, "xlnx.zdma");
+ s->lpd.iou.adma[i] = SYS_BUS_DEVICE(dev);
+ object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fatal);
+ qdev_init_nofail(dev);
+
+ mr = sysbus_mmio_get_region(s->lpd.iou.adma[i], 0);
+ memory_region_add_subregion(&s->mr_ps,
+ MM_ADMA_CH0 + i * MM_ADMA_CH0_SIZE, mr);
+
+ sysbus_connect_irq(s->lpd.iou.adma[i], 0, pic[VERSAL_ADMA_IRQ_0 + i]);
+ g_free(name);
+ }
+}
+
/* This takes the board allocated linear DDR memory and creates aliases
* for each split DDR range/aperture on the Versal address map.
*/
versal_create_apu_gic(s, pic);
versal_create_uarts(s, pic);
versal_create_gems(s, pic);
+ versal_create_admas(s, pic);
versal_map_ddr(s);
versal_unimp(s);
#define XLNX_VERSAL_NR_ACPUS 2
#define XLNX_VERSAL_NR_UARTS 2
#define XLNX_VERSAL_NR_GEMS 2
+#define XLNX_VERSAL_NR_ADMAS 8
#define XLNX_VERSAL_NR_IRQS 192
typedef struct Versal {
struct {
SysBusDevice *uart[XLNX_VERSAL_NR_UARTS];
SysBusDevice *gem[XLNX_VERSAL_NR_GEMS];
+ SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS];
} iou;
} lpd;
#define VERSAL_GEM0_WAKE_IRQ_0 57
#define VERSAL_GEM1_IRQ_0 58
#define VERSAL_GEM1_WAKE_IRQ_0 59
+#define VERSAL_ADMA_IRQ_0 60
/* Architecturally reserved IRQs suitable for virtualization. */
#define VERSAL_RSVD_IRQ_FIRST 111
#define MM_GEM1 0xff0d0000U
#define MM_GEM1_SIZE 0x10000
+#define MM_ADMA_CH0 0xffa80000U
+#define MM_ADMA_CH0_SIZE 0x10000
+
#define MM_OCM 0xfffc0000U
#define MM_OCM_SIZE 0x40000