hmp: Add "calc_dirty_rate" and "info dirty_rate" cmds

These two commands are missing when adding the QMP sister commands.
Add them, so developers can play with them easier.

Signed-off-by: Peter Xu <[email protected]>
Signed-off-by: Hyman Huang(黄勇) <[email protected]>
Message-Id: <4cc0039fc3ad6145136770cf3b0f056c09a2910b.1623027729[email protected]>
Reviewed-by: Dr. David Alan Gilbert <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

migration/dirtyrate: make sample page count configurable

introduce optional sample-pages argument in calc-dirty-rate,
making sample page count per GB configurable so that more
accurate dirtyrate can be calculated.

Signed-off-by: Hyman Huang(黄勇) <[email protected]>
Message-Id: <3103453a3b2796f929269c99a6ad81a9a7f1f405.1623027729[email protected]>
Reviewed-by: Dr. David Alan Gilbert <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>
  Wrapped a couple of long lines

sockets: Support multipath TCP

Multipath TCP allows combining multiple interfaces/routes into a single
socket, with very little work for the user/admin.

It's enabled by 'mptcp' on most socket addresses:

   ./qemu-system-x86_64 -nographic -incoming tcp:0:4444,mptcp

Signed-off-by: Dr. David Alan Gilbert <[email protected]>
Message-Id: <20210421112834[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

migration/socket: Close the listener at the end

Delay closing the listener until the cleanup hook at the end; mptcp
needs the listener to stay open while the other paths come in.

Signed-off-by: Dr. David Alan Gilbert <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-Id: <20210421112834[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

migration: Add cleanup hook for inwards migration

Add a cleanup hook for incoming migration that gets called
at the end as a way for a transport to allow cleanup.

Signed-off-by: Dr. David Alan Gilbert <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-Id: <20210421112834[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

io/net-listener: Call the notifier during finalize

Call the notifier during finalize; it's currently only called
if we change it, which is not the intent.

Signed-off-by: Dr. David Alan Gilbert <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-Id: <20210421112834[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

channel-socket: Only set CLOEXEC if we have space for fds

MSG_CMSG_CLOEXEC cleans up received fd's; it's really only for Unix
sockets, but currently we enable it for everything; some socket types
(IP_MPTCP) don't like this.

Only enable it when we're giving the recvmsg room to receive fd's
anyway.

Signed-off-by: Dr. David Alan Gilbert <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Message-Id: <20210421112834[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

migration/rdma: Fix cm event use after free

Signed-off-by: Li Zhijian <[email protected]>
Message-Id: <20210602023506.3821293[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>
Reviewed-by: Dr. David Alan Gilbert <[email protected]>

yank: Unregister function when using TLS migration

After yank feature was introduced in migration, whenever migration
is started using TLS, the following error happens in both source and
destination hosts:

(qemu) qemu-kvm: ../util/yank.c:107: yank_unregister_instance:
Assertion `QLIST_EMPTY(&entry->yankfns)' failed.

This happens because of a missing yank_unregister_function() when using
qio-channel-tls.

Fix this by also allowing TYPE_QIO_CHANNEL_TLS object type to perform
yank_unregister_function() in channel_close() and multifd_load_cleanup().

Also, inside migration_channel_connect() and
migration_channel_process_incoming() move yank_register_function() so
it only runs once on a TLS migration.

Fixes: b5eea99ec2f ("migration: Add yank feature", 2021-01-13)
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1964326
Signed-off-by: Leonardo Bras <[email protected]>
Reviewed-by: Lukas Straub <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
--
Changes since v2:
- Dropped all references to ioc->master
- yank_register_function() and yank_unregister_function() now only run
  once in a TLS migration.

Changes since v1:
- Cast p->c to QIOChannelTLS into multifd_load_cleanup()
Message-Id: <20210601054030.1153249[email protected]>

Signed-off-by: Dr. David Alan Gilbert <[email protected]>

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20210608-1' into staging

Second RISC-V PR for QEMU 6.1

 - Update the PLIC and CLINT DT bindings
 - Improve documentation for RISC-V machines
 - Support direct kernel boot for microchip_pfsoc
 - Fix WFI exception behaviour
 - Improve CSR printing
 - Initial support for the experimental Bit Manip extension

# gpg: Signature made Tue 08 Jun 2021 01:28:27 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <[email protected]>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20210608-1: (32 commits)
  target/riscv: rvb: add b-ext version cpu option
  target/riscv: rvb: support and turn on B-extension from command line
  target/riscv: rvb: add/shift with prefix zero-extend
  target/riscv: rvb: address calculation
  target/riscv: rvb: generalized or-combine
  target/riscv: rvb: generalized reverse
  target/riscv: rvb: rotate (left/right)
  target/riscv: rvb: shift ones
  target/riscv: rvb: single-bit instructions
  target/riscv: add gen_shifti() and gen_shiftiw() helper functions
  target/riscv: rvb: sign-extend instructions
  target/riscv: rvb: min/max instructions
  target/riscv: rvb: pack two words into one register
  target/riscv: rvb: logic-with-negate
  target/riscv: rvb: count bits set
  target/riscv: rvb: count leading/trailing zeros
  target/riscv: reformat @sh format encoding for B-extension
  target/riscv: Pass the same value to oprsz and maxsz.
  target/riscv/pmp: Add assert for ePMP operations
  target/riscv: Dump CSR mscratch/sscratch/satp
  ...

Signed-off-by: Peter Maydell <[email protected]>

target/riscv: rvb: add b-ext version cpu option

Default b-ext version is v0.93.

Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: support and turn on B-extension from command line

B-extension is default off, use cpu rv32 or rv64 with x-b=true to
enable B-extension.

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: add/shift with prefix zero-extend

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: address calculation

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: generalized or-combine

Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: generalized reverse

Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: rotate (left/right)

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: shift ones

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: single-bit instructions

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: add gen_shifti() and gen_shiftiw() helper functions

Add gen_shifti() and gen_shiftiw() helper functions to reuse the same
interfaces for immediate shift instructions.

Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: sign-extend instructions

Signed-off-by: Kito Cheng <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: min/max instructions

Signed-off-by: Kito Cheng <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: pack two words into one register

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: logic-with-negate

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: count bits set

Signed-off-by: Kito Cheng <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: rvb: count leading/trailing zeros

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: reformat @sh format encoding for B-extension

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: Pass the same value to oprsz and maxsz.

Since commit e2e7168a214b0ed98dc357bba96816486a289762, if oprsz
is still zero(as we don't use this field), simd_desc will trigger an
assert.

Besides, tcg_gen_gvec_*_ptr calls simd_desc in it's implementation.
Here we pass the value to maxsz and oprsz to bypass the assert.

Signed-off-by: LIU Zhiwei <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 20210521054816.1784297[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv/pmp: Add assert for ePMP operations

Although we construct epmp_operation in such a way that it can only be
between 0 and 15 Coverity complains that we don't handle the other
possible cases. To fix Coverity and make it easier for humans to read
add a default case to the switch statement that calls
g_assert_not_reached().

Fixes: CID 1453108
Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Message-id: ec5f225928eec448278c82fcb1f6805ee61dde82.1621550996[email protected]

target/riscv: Dump CSR mscratch/sscratch/satp

This dumps the CSR mscratch/sscratch/satp and meanwhile aligns
the output of CSR mtval/stval.

Signed-off-by: Changbin Du <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Message-id: 20210519155738[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: Remove unnecessary riscv_*_names[] declaration

riscv_excp_names[] and riscv_intr_names[] are only referenced by
target/riscv/cpu.c locally.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210514052435.2203156[email protected]
Signed-off-by: Alistair Francis <[email protected]>

target/riscv: Do not include 'pmp.h' in user emulation

Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Message-id: 20210516205333[email protected]
Signed-off-by: Alistair Francis <[email protected]>

docs/system: Move the RISC-V -bios information to removed

QEMU 5.1 changed the behaviour of the default boot for the RISC-V virt
and sifive_u machines. This patch moves that change from the
deprecated.rst file to the removed-features.rst file and the
target-riscv.rst.

Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Message-id: 4f1c261e7f69045ab8bb8926d85fe1d35e48ea5b.1620081256[email protected]

target/riscv: fix wfi exception behavior

The wfi exception trigger behavior should take into account user mode,
hstatus.vtw, and the fact the an wfi might raise different types of
exceptions depending on various factors:

If supervisor mode is not present:

- an illegal instruction exception should be generated if user mode
executes and wfi instruction and mstatus.tw = 1.

If supervisor mode is present:

- when a wfi instruction is executed, an illegal exception should be triggered
if either the current mode is user or the mode is supervisor and mstatus.tw is
set.

Plus, if the hypervisor extensions are enabled:

- a virtual instruction exception should be raised when a wfi is executed from
virtual-user or virtual-supervisor and hstatus.vtw is set.

Signed-off-by: Jose Martins <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210420213656[email protected]
Signed-off-by: Alistair Francis <[email protected]>

hw/riscv: microchip_pfsoc: Support direct kernel boot

At present the Microchip Icicle Kit machine only supports using
'-bios' to load the HSS, and does not support '-kernel' for direct
kernel booting just like other RISC-V machines do. One has to use
U-Boot which is chain-loaded by HSS, to load a kernel for testing.
This is not so convenient.

Adding '-kernel' support together with the existing '-bios', we
follow the following table to select which payload we execute:

  -bios |    -kernel | payload
  ------+------------+--------
      N |          N | HSS
      Y | don't care | HSS
      N |          Y | kernel

This ensures backwards compatibility with how we used to expose
'-bios' to users. When '-kernel' is used for direct boot, '-dtb'
must be present to provide a valid device tree for the board,
as we don't generate device tree.

When direct kernel boot is used, the OpenSBI fw_dynamic BIOS image
is used to boot a payload like U-Boot or OS kernel directly.

Documentation is updated to describe the direct kernel boot. Note
as of today there is still no PolarFire SoC support in the upstream
Linux kernel hence the document does not include instructions for
that. It will be updated in the future.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210430071302.1489082[email protected]
Signed-off-by: Alistair Francis <[email protected]>

hw/riscv: Use macros for BIOS image names

The OpenSBI BIOS image names are used by many RISC-V machines.
Let's define macros for them.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210430071302.1489082[email protected]
Signed-off-by: Alistair Francis <[email protected]>

docs/system/riscv: sifive_u: Document '-dtb' usage

Update the 'sifive_u' machine documentation to mention the '-dtb'
option that can be used to pass a custom DTB to QEMU.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210430071302.1489082[email protected]
Signed-off-by: Alistair Francis <[email protected]>

docs/system/riscv: Correct the indentation level of supported devices

The supported device bullet list has an additional space before each
entry, which makes a wrong indentation level. Correct it.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210430071302.1489082[email protected]
Signed-off-by: Alistair Francis <[email protected]>

hw/riscv: Support the official PLIC DT bindings

The official DT bindings of PLIC uses "sifive,plic-1.0.0" as the
compatible string in the upstream Linux kernel. "riscv,plic0" is
now legacy and has to be kept for backward compatibility of legacy
systems.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210430071302.1489082[email protected]
Signed-off-by: Alistair Francis <[email protected]>

hw/riscv: Support the official CLINT DT bindings

Linux kernel commit a2770b57d083 ("dt-bindings: timer: Add CLINT bindings")
adds the official DT bindings for CLINT, which uses "sifive,clint0"
as the compatible string. "riscv,clint0" is now legacy and has to
be kept for backward compatibility of legacy systems.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210430071302.1489082[email protected]
Signed-off-by: Alistair Francis <[email protected]>

hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper

Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"),
we can use the new helper to set the compatible strings for the
SiFive test device node.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210430071302.1489082[email protected]
Signed-off-by: Alistair Francis <[email protected]>

hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper

Since commit 78da6a1bca22 ("device_tree: add qemu_fdt_setprop_string_array helper"),
we can use the new helper to set the clock name for the ethernet
controller node.

Signed-off-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210430071302.1489082[email protected]
Signed-off-by: Alistair Francis <[email protected]>

Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging

Trivial branch pull request 20210607

# gpg: Signature made Mon 07 Jun 2021 19:56:43 BST
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Laurent Vivier <[email protected]>" [full]
# gpg:                 aka "Laurent Vivier <[email protected]>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <[email protected]>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/trivial-branch-for-6.1-pull-request:
  vhost-vdpa: Remove redundant declaration of address_space_memory
  scripts/oss-fuzz: Fix typo in documentation
  target/mips: Fix 'Uncoditional' typo
  target/hppa: Remove unused 'memory.h' header
  hw/display/macfb: Classify the "nubus-macfb" as display device
  target/nios2: fix page-fit instruction count
  docs: fix broken reference
  linux-user/syscall: Constify bitmask_transtbl fcntl/mmap flags_tlb[]
  misc: Correct relative include path
  i386/kvm: The value passed to strerror should be positive
  target/riscv: Do not include 'pmp.h' in user emulation

Signed-off-by: Peter Maydell <[email protected]>

Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging

A few testing and configure updates:

  - add the multiarch signals stress test
  - fix display of multi-word compiler stanzas in meson
  - fix quoting of multi-word compiler stazas in configure.sh
  - tag some acceptance tests as TCG only
  - make checkpatch test work harder to find clean diffs
  - split gprof/gconv job to avoid timeouts
  - fix centos8 VM build by adding --source-path
  - make checkpatch aware of .h.inc and .c.inc paths

# gpg: Signature made Mon 07 Jun 2021 14:51:12 BST
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# gpg: Good signature from "Alex Bennée (Master Work Key) <[email protected]>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-testing-updates-070621-2:
  scripts/checkpatch.pl: process .c.inc and .h.inc files as C source
  tests/vm: expose --source-path to scripts to find extra files
  gitlab-ci: Split gprof-gcov job
  gitlab: work harder to avoid false positives in checkpatch
  tests/acceptance: tag various arm tests as TCG only
  tests/tcg/configure.sh: tweak quoting of target_compiler
  meson.build: fix cosmetics of compiler display
  tests/tcg: add a multiarch signals test to stress test signal delivery

Signed-off-by: Peter Maydell <[email protected]>

scripts/checkpatch.pl: process .c.inc and .h.inc files as C source

Change the regex used to determine whether a file should be processed as
C source to include .c.inc and .h.inc extensions.

Signed-off-by: Matheus Ferst <[email protected]>
Reviewed-by: Luis Pires <[email protected]>
Message-Id: <20210520195142[email protected]>
Signed-off-by: Alex Bennée <[email protected]>

tests/vm: expose --source-path to scripts to find extra files

Currently the centos8 image expects to run an in-src build to find the
kick starter file. Fix this.

Signed-off-by: Alex Bennée <[email protected]>
Message-Id: <20210602103527[email protected]>

gitlab-ci: Split gprof-gcov job

This job is hitting the 70min limit, so split it in 2 tasks.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Willian Rampazzo <[email protected]>
Message-Id: <20210525082556.4011380[email protected]>

gitlab: work harder to avoid false positives in checkpatch

This copies the behaviour of patchew's configuration to make the diff
algorithm generate a minimal diff.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Wainer dos Santos Moschetta <[email protected]>
Message-Id: <20210602153247[email protected]>

tests/acceptance: tag various arm tests as TCG only

We should never be trying to run most of these models under a KVM
environment.

Signed-off-by: Alex Bennée <[email protected]>
Tested-by: Willian Rampazzo <[email protected]>
Message-Id: <20210527160319[email protected]>

tests/tcg/configure.sh: tweak quoting of target_compiler

If you configure the host compiler with a multi-command stanza like:

  --cc="ccache gcc"

then the configure.sh machinery falls over with confusion. Work around
this by ensuring we correctly quote so where we need a complete
evaluation we get it. Of course the has() check needs single variable
so we need to unquote that. This does mean it essentially checks that
just the ccache command exits but if we got past that step we still
check the compiler actually does something.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Cc: Thomas Huth <[email protected]>
Message-Id: <20210527160319[email protected]>

meson.build: fix cosmetics of compiler display

If you specify something like --cc="ccache gcc" on your configure line
the summary output misses the rest of the cmd_array. Do some string
joining to make it complete.

Signed-off-by: Alex Bennée <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20210527160319[email protected]>

tests/tcg: add a multiarch signals test to stress test signal delivery

This adds a simple signal test that combines the POSIX timer_create
with signal delivery across multiple threads. The aim is to provide a
bit more of a stress test to flush out signal handling issues for
easily than the occasional random crash we sometimes see in linux-test
or threadcount.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20210527160319[email protected]>

vhost-vdpa: Remove redundant declaration of address_space_memory

The symbol address_space_memory are already declared in
include/exec/address-spaces.h. So let's add this header file
and remove the redundant declaration in include/hw/virtio/vhost-vdpa.h.

Signed-off-by: Xie Yongji <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Stefano Garzarella <[email protected]>
Message-Id: <20210517123246[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

scripts/oss-fuzz: Fix typo in documentation

While we only use stdin, the chardev is named 'stdio'.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alexander Bulekov <[email protected]>
Message-Id: <20210602170759.2500248[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

target/mips: Fix 'Uncoditional' typo

Fix Uncoditional -> Unconditional typo.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Luis Pires <[email protected]>
Message-Id: <20210602170759.2500248[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

target/hppa: Remove unused 'memory.h' header

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <20210517101558.1040191[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

hw/display/macfb: Classify the "nubus-macfb" as display device

The "nubus-macfb" currently shows up as uncategorized device in
the output of "-device help". Put it into the display category
to fix this ugliness.

Signed-off-by: Thomas Huth <[email protected]>
Reviewed-by: Laurent Vivier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210531073255[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

target/nios2: fix page-fit instruction count

This patch fixes calculation of number of the instructions
that fit the current page. It prevents creation of the translation
blocks that cross the page boundaries. It is required for deterministic
exception generation in icount mode.

Signed-off-by: Pavel Dovgalyuk <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <162072241046.823357.10485774346114851009.stgit@pasha-ThinkPad-X280>
Signed-off-by: Laurent Vivier <[email protected]>

docs: fix broken reference

Long story short, we need a space here for the reference to work
correctly.

Longer story:

Without the space, kerneldoc generates a line like this:

one of :c:type:`MemoryListener.region_add\(\) <MemoryListener>`,:c:type:`MemoryListener.region_del\(\)

Sphinx does not process the role information correctly, so we get this
(my pseudo-notation) construct:

<text>,:c:type:</text>
<reference target="MemoryListener">MemoryListener.region_del()</reference>

which does not reference the desired entity, and leaves some extra junk
in the rendered output. See
https://qemu-project.gitlab.io/qemu/devel/memory.html#c.MemoryListener
member log_start for an example of the broken output as it looks today.

Signed-off-by: John Snow <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-Id: <20210511192950.2061326[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

linux-user/syscall: Constify bitmask_transtbl fcntl/mmap flags_tlb[]

Keep bitmask_transtbl in .rodata by marking the arrays const.

Reviewed-by: Laurent Vivier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <20210517055243[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

misc: Correct relative include path

Headers should be included from the 'include/' directory,
not from the root directory.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Message-Id: <20210516205034[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

i386/kvm: The value passed to strerror should be positive

Signed-off-by: Dmitry Voronetskiy <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Message-Id: <20210519113528[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

target/riscv: Do not include 'pmp.h' in user emulation

Physical Memory Protection is a system feature.
Avoid polluting the user-mode emulation by its definitions.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-Id: <20210516205333[email protected]>
Signed-off-by: Laurent Vivier <[email protected]>

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210604' into staging

Host vector support for arm neon.

# gpg: Signature made Fri 04 Jun 2021 19:56:59 BST
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* remotes/rth-gitlab/tags/pull-tcg-20210604:
  tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
  tcg/arm: Implement TCG_TARGET_HAS_roti_vec
  tcg/arm: Implement TCG_TARGET_HAS_shv_vec
  tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
  tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
  tcg/arm: Implement TCG_TARGET_HAS_sat_vec
  tcg/arm: Implement TCG_TARGET_HAS_mul_vec
  tcg/arm: Implement TCG_TARGET_HAS_shi_vec
  tcg/arm: Implement andc, orc, abs, neg, not vector operations
  tcg/arm: Implement minimal vector operations
  tcg/arm: Implement tcg_out_dup*_vec
  tcg/arm: Implement tcg_out_mov for vector types
  tcg/arm: Implement tcg_out_ld/st for vector types
  tcg/arm: Add host vector framework
  tcg: Change parameters for tcg_target_const_match

Signed-off-by: Peter Maydell <[email protected]>

tcg/arm: Implement TCG_TARGET_HAS_rotv_vec

Implement via expansion, so don't actually set TCG_TARGET_HAS_rotv_vec.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement TCG_TARGET_HAS_roti_vec

Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement TCG_TARGET_HAS_shv_vec

The three vector shift by vector operations are all implemented via
expansion.  Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec

NEON has 3 instructions implementing this 4 argument operation,
with each insn overlapping a different logical input onto the
destination register.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement TCG_TARGET_HAS_minmax_vec

This is minimum and maximum, signed and unsigned.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement TCG_TARGET_HAS_sat_vec

This is saturating add and subtract, signed and unsigned.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement TCG_TARGET_HAS_mul_vec

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement TCG_TARGET_HAS_shi_vec

This consists of the three immediate shifts: shli, shri, sari.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement andc, orc, abs, neg, not vector operations

These logical and arithmetic operations are optional, but are
trivial to accomplish with the existing infrastructure.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement minimal vector operations

Implementing dup2, add, sub, and, or, xor as the minimal set.
This allows us to actually enable neon in the header file.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement tcg_out_dup*_vec

Most of dupi is copied from tcg/aarch64, which has the same
encoding for AdvSimdExpandImm.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement tcg_out_mov for vector types

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Implement tcg_out_ld/st for vector types

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg/arm: Add host vector framework

Add registers and function stubs.  The functionality
is disabled via use_neon_instructions defined to 0.

We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

tcg: Change parameters for tcg_target_const_match

Change the return value to bool, because that's what is should
have been from the start.  Pass the ct mask instead of the whole
TCGArgConstraint, as that's the only part that's relevant.

Change the value argument to int64_t.  We will need the extra
width for 32-bit hosts wanting to match vector constants.

Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>

Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

* OpenBSD cleanup (Brad)
* fixes for the i386 accel/cpu refactoring (Claudio)
* unmap test for emulated SCSI (Kit)
* fix for iscsi module (myself)
* fix for -readconfig of objects (myself)
* fixes for x86 16-bit task switching (myself)
* fix for x86 MOV from/to CR8 (Richard)

# gpg: Signature made Fri 04 Jun 2021 12:53:32 BST
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* remotes/bonzini-gitlab/tags/for-upstream:
  vl: plug -object back into -readconfig
  vl: plumb keyval-based options into -readconfig
  qemu-config: parse configuration files to a QDict
  i386: run accel_cpu_instance_init as post_init
  i386: reorder call to cpu_exec_realizefn
  tests/qtest/virtio-scsi-test: add unmap large LBA with 4k blocks test
  target/i386: Fix decode of cr8
  target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa
  target/i386: tcg: fix loading of registers from 16-bit TSS
  target/i386: tcg: fix segment register offsets for 16-bit TSS
  oslib-posix: Remove OpenBSD workaround for fcntl("/dev/null", F_SETFL, O_NONBLOCK) failure
  iscsi: link libm into the module
  meson: allow optional dependencies for block modules

Signed-off-by: Peter Maydell <[email protected]>

Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging

# gpg: Signature made Fri 04 Jun 2021 08:26:16 BST
# gpg:                using RSA key EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <[email protected]>" [marginal]
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# Primary key fingerprint: 215D 46F4 8246 689E C77F  3562 EF04 965B 398D 6211

* remotes/jasowang/tags/net-pull-request:
  MAINTAINERS: Added eBPF maintainers information.
  docs: Added eBPF documentation.
  virtio-net: Added eBPF RSS to virtio-net.
  ebpf: Added eBPF RSS loader.
  ebpf: Added eBPF RSS program.
  net: Added SetSteeringEBPF method for NetClientState.
  net/tap: Added TUNSETSTEERINGEBPF code.

Signed-off-by: Peter Maydell <[email protected]>

vl: plug -object back into -readconfig

Commit bc2f4fcb1d ("qom: move user_creatable_add_opts logic to vl.c
and QAPIfy it", 2021-03-19) switched the creation of objects from
qemu_opts_foreach to a bespoke QTAILQ in preparation for supporting JSON
syntax in -object.

Unfortunately in doing so it lost support for [object] stanzas in
configuration files and also for "-set object.ID.KEY=VAL".  The latter
is hard to re-establish and probably best solved by deprecating -set.
This patch uses the infrastructure introduced by the previous two
patches in order to parse QOM objects correctly from configuration
files.

Cc: Markus Armbruster <[email protected]>
Cc: [email protected]
Reviewed-by: Kevin Wolf <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Message-Id: <20210524105752.3318299[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

vl: plumb keyval-based options into -readconfig

Let -readconfig support parsing command line options into QDict or
QemuOpts.  This will be used to add back support for objects in
-readconfig.

Cc: Markus Armbruster <[email protected]>
Cc: [email protected]
Reviewed-by: Kevin Wolf <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Message-Id: <20210524105752.3318299[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

qemu-config: parse configuration files to a QDict

Change the parser to put the values into a QDict and pass them
to a callback.  qemu_config_parse's QemuOpts creation is
itself turned into a callback function.

This is useful for -readconfig to support keyval-based options;
getting a QDict from the parser removes a roundtrip from
QDict to QemuOpts and then back to QDict.

Unfortunately there is a disadvantage in that semantic errors will
point to the last line of the group, because the entries of the QDict
do not have a location attached.

Cc: Kevin Wolf <[email protected]>
Cc: Markus Armbruster <[email protected]>
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Message-Id: <20210524105752.3318299[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

i386: run accel_cpu_instance_init as post_init

This fixes host and max cpu initialization, by running the accel cpu
initialization only after all instance init functions are called for all
X86 cpu subclasses.

The bug this is fixing is related to the "max" and "host" i386 cpu
subclasses, which set cpu->max_features, which is then used at cpu
realization time.

In order to properly split the accel-specific max features code that
needs to be executed at cpu instance initialization time,

we cannot call the accel cpu initialization at the end of the x86 base
class initialization, or we will have no way to specialize
"max features" cpu behavior, overriding the "max" cpu class defaults,
and checking for the "max features" flag itself.

This patch moves the accel-specific cpu instance initialization to after
all x86 cpu instance code has been executed, including subclasses,

so that proper initialization of cpu "host" and "max" can be restored.

Fixes: f5cc5a5c ("i386: split cpu accelerators from cpu.c,"...)
Cc: Eduardo Habkost <[email protected]>
Cc: Paolo Bonzini <[email protected]>
Signed-off-by: Claudio Fontana <[email protected]>
Message-Id: <20210603123001[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

i386: reorder call to cpu_exec_realizefn

i386 realizefn code is sensitive to ordering, and recent commits
aimed at refactoring it, splitting accelerator-specific code,
broke assumptions which need to be fixed.

We need to:

* process hyper-v enlightements first, as they assume features
  not to be expanded

* only then, expand features

* after expanding features, attempt to check them and modify them in the
  accel-specific realizefn code called by cpu_exec_realizefn().

* after the framework has been called via cpu_exec_realizefn,
  the code can check for what has or hasn't been set by accel-specific
  code, or extend its results, ie:

  - check and evenually set code_urev default
  - modify cpu->mwait after potentially being set from host CPUID.
  - finally check for phys_bits assuming all user and accel-specific
    adjustments have already been taken into account.

Fixes: f5cc5a5c ("i386: split cpu accelerators from cpu.c"...)
Fixes: 30565f10 ("cpu: call AccelCPUClass::cpu_realizefn in"...)
Cc: Eduardo Habkost <[email protected]>
Cc: Vitaly Kuznetsov <[email protected]>
Cc: Paolo Bonzini <[email protected]>
Signed-off-by: Claudio Fontana <[email protected]>
Message-Id: <20210603123001[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

tests/qtest/virtio-scsi-test: add unmap large LBA with 4k blocks test

Add test for issue #345

Signed-off-by: Kit Westneat <[email protected]>
Message-Id: <20210603142022[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

target/i386: Fix decode of cr8

A recent cleanup did not recognize that there are two ways
to encode cr8: one via the LOCK and the other via REX.

Fixes: 7eff2e7c
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/380
Signed-off-by: Richard Henderson <[email protected]>
Message-Id: <20210602035511[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa

The format of the task state segment is governed by bit 3 in the
descriptor type field.  On a task switch, the format for saving
is given by the current value of TR's type field, while the
format for loading is given by the new descriptor.

Signed-off-by: Paolo Bonzini <[email protected]>

target/i386: tcg: fix loading of registers from 16-bit TSS

According to the manual, the high 16-bit of the registers are preserved
when switching to a 16-bit task.  Implement this in switch_tss_ra.

Signed-off-by: Paolo Bonzini <[email protected]>

target/i386: tcg: fix segment register offsets for 16-bit TSS

The TSS offsets in the manuals have only 2-byte slots for the
segment registers.  QEMU incorrectly uses 4-byte slots, so
that SS overlaps the LDT selector.

Resolves: #382
Reported-by: Peter Maydell <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

oslib-posix: Remove OpenBSD workaround for fcntl("/dev/null", F_SETFL, O_NONBLOCK) failure

OpenBSD prior to 6.3 required a workaround to utilize fcntl(F_SETFL) on memory
devices.

Since modern verions of OpenBSD that are only officialy supported and buildable
on do not have this issue I am garbage collecting this workaround.

Signed-off-by: Brad Smith <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

iscsi: link libm into the module

Depending on the configuration of QEMU, some binaries might not need libm
at all.  In that case libiscsi, which uses exp(), will fail to load.
Link it in the module explicitly.

Reported-by: Yi Sun <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>

meson: allow optional dependencies for block modules

Right now all dependencies for block modules are passed to
module_ss.add(when: ...), so they are mandatory.  In the next patch we
will need to add a libm dependency to a module, but libm does not exist
on all systems.  So, modify the creation of module_ss and modsrc so that
dependencies can also be passed to module_ss.add(if_true: ...).

While touching the array, remove the useless dependency of the curl
module on glib.  glib is always linked in QEMU and in fact all other
block modules also need it, but they don't have to specify it.

Signed-off-by: Paolo Bonzini <[email protected]>

Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-fpu-20210603' into staging

Finish conversion of float128 and floatx80 to FloatParts.
Implement float128_muladd and float128_{min,max}*.
Optimize int-to-float conversion with hard-float.

# gpg: Signature made Thu 03 Jun 2021 22:13:10 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth-gitlab/tags/pull-fpu-20210603: (29 commits)
  softfloat: Use hard-float for {u}int64_to_float{32,64}
  tests/fp: Enable more tests
  softfloat: Convert modrem operations to FloatParts
  softfloat: Move floatN_log2 to softfloat-parts.c.inc
  softfloat: Convert float32_exp2 to FloatParts
  softfloat: Convert floatx80 compare to FloatParts
  softfloat: Convert floatx80_scalbn to FloatParts
  softfloat: Convert floatx80 to integer to FloatParts
  softfloat: Convert floatx80 float conversions to FloatParts
  softfloat: Convert integer to floatx80 to FloatParts
  softfloat: Convert floatx80_round_to_int to FloatParts
  softfloat: Convert floatx80_round to FloatParts
  softfloat: Convert floatx80_sqrt to FloatParts
  softfloat: Convert floatx80_div to FloatParts
  softfloat: Convert floatx80_mul to FloatParts
  softfloat: Convert floatx80_add/sub to FloatParts
  tests/fp/fp-test: Reverse order of floatx80 precision tests
  softfloat: Adjust parts_uncanon_normal for floatx80
  softfloat: Introduce Floatx80RoundPrec
  softfloat: Reduce FloatFmt
  ...

Signed-off-by: Peter Maydell <[email protected]>

MAINTAINERS: Added eBPF maintainers information.

Signed-off-by: Yuri Benditovich <[email protected]>
Signed-off-by: Andrew Melnychenko <[email protected]>
Signed-off-by: Jason Wang <[email protected]>

docs: Added eBPF documentation.

Signed-off-by: Yuri Benditovich <[email protected]>
Signed-off-by: Andrew Melnychenko <[email protected]>
Signed-off-by: Jason Wang <[email protected]>

virtio-net: Added eBPF RSS to virtio-net.

When RSS is enabled the device tries to load the eBPF program
to select RX virtqueue in the TUN. If eBPF can be loaded
the RSS will function also with vhost (works with kernel 5.8 and later).
Software RSS is used as a fallback with vhost=off when eBPF can't be loaded
or when hash population requested by the guest.

Signed-off-by: Yuri Benditovich <[email protected]>
Signed-off-by: Andrew Melnychenko <[email protected]>
Signed-off-by: Jason Wang <[email protected]>

ebpf: Added eBPF RSS loader.

Added function that loads RSS eBPF program.
Added stub functions for RSS eBPF loader.
Added meson and configuration options.

By default, eBPF feature enabled if libbpf is present in the build system.
libbpf checked in configuration shell script and meson script.

Signed-off-by: Yuri Benditovich <[email protected]>
Signed-off-by: Andrew Melnychenko <[email protected]>
Signed-off-by: Jason Wang <[email protected]>

ebpf: Added eBPF RSS program.

RSS program and Makefile to build it.
The bpftool used to generate '.h' file.
The data in that file may be loaded by libbpf.
EBPF compilation is not required for building qemu.
You can use Makefile if you need to regenerate rss.bpf.skeleton.h.

Signed-off-by: Yuri Benditovich <[email protected]>
Signed-off-by: Andrew Melnychenko <[email protected]>
Signed-off-by: Jason Wang <[email protected]>