]> Git Repo - qemu.git/commit
target/riscv: rvb: count leading/trailing zeros
authorKito Cheng <[email protected]>
Wed, 5 May 2021 16:06:03 +0000 (00:06 +0800)
committerAlistair Francis <[email protected]>
Mon, 7 Jun 2021 23:59:43 +0000 (09:59 +1000)
commit438240185a9456747b19a29290018316271a3762
tree61d4bf60b5f37ae5f813673155fa163265725af4
parent00718208c127315d82f1f1f8383ef29bc478628e
target/riscv: rvb: count leading/trailing zeros

Signed-off-by: Kito Cheng <[email protected]>
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-id: 20210505160620[email protected]
Signed-off-by: Alistair Francis <[email protected]>
target/riscv/cpu.h
target/riscv/insn32.decode
target/riscv/insn_trans/trans_rvb.c.inc [new file with mode: 0644]
target/riscv/translate.c
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