James Hogan [Tue, 18 Jul 2017 11:55:57 +0000 (12:55 +0100)]
target/mips: Implement segmentation control
Implement the optional segmentation control feature in the virtual to
physical address translation code.
The fixed legacy segment and xkphys handling is replaced with a dynamic
layout based on the segmentation control registers (which should be set
up even when the feature is not exposed to the guest).
James Hogan [Tue, 18 Jul 2017 11:55:56 +0000 (12:55 +0100)]
target/mips: Add segmentation control registers
The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 &
CP0_SegCtl2 control the behaviour and required privilege of the legacy
virtual memory segments.
Add them to the CP0 interface so they can be read and written when
CP0_Config3.SC=1, and initialise them to describe the standard legacy
layout so they can be used in future patches regardless of whether they
are exposed to the guest.
James Hogan [Tue, 18 Jul 2017 11:55:55 +0000 (12:55 +0100)]
target/mips: Add an MMU mode for ERL
The segmentation control feature allows a legacy memory segment to
become unmapped uncached at error level (according to CP0_Status.ERL),
and in fact the user segment is already treated in this way by QEMU.
Add a new MMU mode for this state so that QEMU's mappings don't persist
between ERL=0 and ERL=1.
James Hogan [Tue, 18 Jul 2017 11:55:54 +0000 (12:55 +0100)]
target/mips: Abstract mmu_idx from hflags
The MIPS mmu_idx is sometimes calculated from hflags without an env
pointer available as cpu_mmu_index() requires.
Create a common hflags_mmu_index() for the purpose of this calculation
which can operate on any hflags, not just with an env pointer, and
update cpu_mmu_index() itself and gen_intermediate_code() to use it.
Also update debug_post_eret() and helper_mtc0_status() to log the MMU
mode with the status change (SM, UM, or nothing for kernel mode) based
on cpu_mmu_index() rather than directly testing hflags.
This will also allow the logic to be more easily updated when a new MMU
mode is added.
James Hogan [Tue, 18 Jul 2017 11:55:53 +0000 (12:55 +0100)]
target/mips: Check memory permissions with mem_idx
When performing virtual to physical address translation, check the
required privilege level based on the mem_idx rather than the mode in
the hflags. This will allow EVA loads & stores to operate safely only on
user memory from kernel mode.
For the cases where the mmu_idx doesn't need to be overridden
(mips_cpu_get_phys_page_debug() and cpu_mips_translate_address()), we
calculate the required mmu_idx using cpu_mmu_index(). Note that this
only tests the MIPS_HFLAG_KSU bits rather than MIPS_HFLAG_MODE, so we
don't test the debug mode hflag MIPS_HFLAG_DM any longer. This should be
fine as get_physical_address() only compares against MIPS_HFLAG_UM and
MIPS_HFLAG_SM, neither of which should get set by compute_hflags() when
MIPS_HFLAG_DM is set.
James Hogan [Tue, 18 Jul 2017 11:55:52 +0000 (12:55 +0100)]
target/mips: Decode microMIPS EVA load & store instructions
Implement decoding of microMIPS EVA load and store instruction groups in
the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond()
helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as
opc.
James Hogan [Tue, 18 Jul 2017 11:55:51 +0000 (12:55 +0100)]
target/mips: Decode MIPS32 EVA load & store instructions
Implement decoding of MIPS32 EVA loads and stores. These access the user
address space from kernel mode when implemented, so for each instruction
we need to check that EVA is available from Config5.EVA & check for
sufficient COP0 privilege (with the new check_eva()), and then override
the mem_idx used for the operation.
Unfortunately some Loongson 2E instructions use overlapping encodings,
so we must be careful not to prevent those from being decoded when EVA
is absent.
James Hogan [Tue, 18 Jul 2017 11:55:50 +0000 (12:55 +0100)]
target/mips: Prepare loads/stores for EVA
EVA load and store instructions access the user mode address map, so
they need to use mem_idx of MIPS_HFLAG_UM. Update the various utility
functions to allow mem_idx to be more easily overridden from the
decoding logic.
Specifically we add a mem_idx argument to the op_ld/st_* helpers used
for atomics, and a mem_idx local variable to gen_ld(), gen_st(), and
gen_st_cond().
James Hogan [Tue, 18 Jul 2017 11:55:49 +0000 (12:55 +0100)]
target/mips: Add CP0_Ebase.WG (write gate) support
Add support for the CP0_EBase.WG bit, which allows upper bits to be
written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the
CP0_Config5.CV bit to control whether the exception vector for Cache
Error exceptions is forced into KSeg1.
This is necessary on MIPS32 to support Segmentation Control and Enhanced
Virtual Addressing (EVA) extensions (where KSeg1 addresses may not
represent an unmapped uncached segment).
It is also useful on MIPS64 to allow the exception base to reside in
XKPhys, and possibly out of range of KSEG0 and KSEG1.
James Hogan [Tue, 18 Jul 2017 11:55:48 +0000 (12:55 +0100)]
target/mips: Weaken TLB flush on UX,SX,KX,ASID changes
There is no need to invalidate any shadow TLB entries when the ASID
changes or when access to one of the 64-bit segments has been disabled,
since doing so doesn't reveal to software whether any TLB entries have
been evicted into the shadow half of the TLB.
Therefore weaken the tlb flushes in these cases to only flush the QEMU
TLB.
James Hogan [Tue, 18 Jul 2017 11:55:47 +0000 (12:55 +0100)]
target/mips: Fix TLBWI shadow flush for EHINV,XI,RI
Writing specific TLB entries with TLBWI flushes shadow TLB entries
unless an existing entry is having its access permissions upgraded. This
is necessary as software would from then on expect the previous mapping
in that entry to no longer be in effect (even if QEMU has quietly
evicted it to the shadow TLB on a TLBWR).
However it won't do this if only EHINV, XI, or RI bits have been set,
even if that results in a reduction of permissions, so add the necessary
checks to invoke the flush when these bits are set.
James Hogan [Tue, 18 Jul 2017 11:55:46 +0000 (12:55 +0100)]
target/mips: Fix MIPS64 MFC0 UserLocal on BE host
Using MFC0 to read CP0_UserLocal uses tcg_gen_ld32s_tl, however
CP0_UserLocal is a target_ulong. On a big endian host with a MIPS64
target this reads and sign extends the more significant half of the
64-bit register.
Fix this by using ld_tl to load the whole target_ulong and ext32s_tl to
sign extend it, as done for various other target_ulong COP0 registers.
Peter Maydell [Fri, 14 Jul 2017 10:45:17 +0000 (11:45 +0100)]
tests: Handle $RANDOM not being supported by the shell
In various places in our test makefiles and scripts we use the
shell $RANDOM to create a random number. This is a bash
specific extension, and doesn't work on other shells.
With dash the shell doesn't complain, it just effectively
always evaluates $RANDOM to 0:
echo $((RANDOM + 32768)) => 32768
However, on NetBSD the shell will complain:
"-sh: arith: syntax error: "RANDOM + 32768"
which means that "make check" fails.
Switch to using "${RANDOM:-0}" instead of $RANDOM,
which will portably either give us a random number or zero.
This means that on non-bash shells we don't get such
good test coverage via the MALLOC_PERTURB_ setting, but
we were already in that situation for non-bash shells.
Our only other uses of $RANDOM (in tests/qemu-iotests/check
and tests/qemu-iotests/162) are in shell scripts which use
a #!/bin/bash line so they are always run under bash.
configure: Don't build ivshmem tools unless CONFIG_IVSHMEM is set
Don't try to build the ivshmem-server and ivshmem-client tools unless
CONFIG_IVSHMEM is set.
This fixes in passing a build bug on NetBSD, which fails to build the
ivshmem tools because they use shm_open() and on NetBSD that requires
linking against -lrt.
configure: Use an explicit CONFIG_IVSHMEM rather than CONFIG_EVENTFD
Rather than relying on everywhere that cares about whether the host
supports ivshmem using CONFIG_EVENTFD, make configure set an explicit
CONFIG_IVSHMEM.
Peter Maydell [Fri, 14 Jul 2017 08:33:43 +0000 (09:33 +0100)]
configure: Rename CONFIG_IVSHMEM to CONFIG_IVSHMEM_DEVICE
The current CONFIG_IVSHMEM is confusing, because it looks like it's a
flag for "do we have ivshmem support?", but actually it's a flag for
"is the ivshmem PCI device being compiled?" (and implicitly "do we
have ivshmem support?" is tested with CONFIG_EVENTFD).
Rename it to CONFIG_IVSHMEM_DEVICE to clear this confusion up;
shortly we will add a new CONFIG_IVSHMEM which really does indicate
whether the host can support ivshmem.
* remotes/rth/tags/pull-tcg-20170719:
tcg: Pass generic CPUState to gen_intermediate_code()
tcg/tci: enable bswap16_i64
target/alpha: optimize gen_cvtlq() using deposit op
target/sparc: optimize gen_op_mulscc() using deposit op
target/sparc: optimize various functions using extract op
target/ppc: optimize various functions using extract op
target/m68k: optimize bcd_flags() using extract op
target/arm: optimize aarch32 rev16
target/arm: Optimize aarch64 rev16
coccinelle: add a script to optimize tcg op using tcg_gen_extract()
coccinelle: ignore ASTs pre-parsed cached C files
tcg: Expand glue macros before stringifying helper names
util/cacheinfo: Add missing include for ppc linux
tcg/mips: reserve a register for the guest_base.
Khem Raj [Wed, 28 Jun 2017 20:44:52 +0000 (13:44 -0700)]
Replace 'struct ucontext' with 'ucontext_t' type
glibc used to have:
typedef struct ucontext { ... } ucontext_t;
glibc now has:
typedef struct ucontext_t { ... } ucontext_t;
(See https://sourceware.org/bugzilla/show_bug.cgi?id=21457
for detail and rationale for the glibc change)
However, QEMU used "struct ucontext" in declarations. This is a
private name and compatibility cannot be guaranteed. Switch to
only using the standardized type name.
Add a .editorconfig file for qemu. Specifies the indent and tab style
for various files (C code and Makefiles for starters). Most popular
editors support this either natively or via plugin.
Their documentation differs, however. According to
change-vnc-password's documentation, "an empty password [...] will set
the password to the empty string", while change's documentation claims
"no future logins will be allowed". The former is actually correct.
Replace the incorrect claim by a reference to change-vnc-password.
Peter Maydell [Wed, 19 Jul 2017 19:45:37 +0000 (20:45 +0100)]
Merge remote-tracking branch 'remotes/berrange/tags/pull-qcrypto-2017-07-18-2' into staging
Merge qcrypto 2017/07/18 v2
# gpg: Signature made Wed 19 Jul 2017 10:11:21 BST
# gpg: using RSA key 0xBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <[email protected]>"
# gpg: aka "Daniel P. Berrange <[email protected]>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF
* remotes/berrange/tags/pull-qcrypto-2017-07-18-2:
tests: crypto: add hmac speed benchmark support
tests: crypto: add hash speed benchmark support
tests: crypto: add cipher speed benchmark support
crypto: hmac: add af_alg-backend hmac support
crypto: hash: add afalg-backend hash support
crypto: cipher: add afalg-backend cipher support
crypto: introduce some common functions for af_alg backend
crypto: hmac: add hmac driver framework
crypto: hmac: introduce qcrypto_hmac_ctx_new for glib-backend
crypto: hmac: introduce qcrypto_hmac_ctx_new for nettle-backend
crypto: hmac: introduce qcrypto_hmac_ctx_new for gcrypt-backend
crypto: hmac: move crypto/hmac.h into include/crypto/
crypto: hash: add hash driver framework
crypto: cipher: add cipher driver framework
crypto: cipher: introduce qcrypto_cipher_ctx_new for builtin-backend
crypto: cipher: introduce qcrypto_cipher_ctx_new for nettle-backend
crypto: cipher: introduce qcrypto_cipher_ctx_new for gcrypt-backend
crypto: cipher: introduce context free function
* remotes/sstabellini/tags/xen-20170718-tag:
xen: don't use xenstore to save/restore physmap anymore
xen/mapcache: introduce xen_replace_cache_entry()
xen/mapcache: add an ability to create dummy mappings
xen: move physmap saving into a separate function
xen-platform: separate unplugging of NVMe disks
xen_pt_msi.c: Check for xen_host_pci_get_* failures in xen_pt_msix_init()
hw/xen: Set emu_mask for igd_opregion register
Peter Maydell [Wed, 19 Jul 2017 13:42:18 +0000 (14:42 +0100)]
Merge remote-tracking branch 'remotes/aurel/tags/pull-target-sh4-20170718' into staging
Queued target/sh4 patches
# gpg: Signature made Tue 18 Jul 2017 22:44:25 BST
# gpg: using RSA key 0xBA9C78061DDD8C9B
# gpg: Good signature from "Aurelien Jarno <[email protected]>"
# gpg: aka "Aurelien Jarno <[email protected]>"
# gpg: aka "Aurelien Jarno <[email protected]>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B
* remotes/aurel/tags/pull-target-sh4-20170718: (31 commits)
target/sh4: Use tcg_gen_lookup_and_goto_ptr
target/sh4: Implement fsrra
target/sh4: Add missing FPSCR.PR == 0 checks
target/sh4: Implement fpchg
target/sh4: Introduce CHECK_SH4A
target/sh4: Introduce CHECK_FPSCR_PR_*
target/sh4: Tidy misc illegal insn checks
target/sh4: Unify code for CHECK_FPU_ENABLED
target/sh4: Unify code for CHECK_PRIVILEGED
target/sh4: Unify code for CHECK_NOT_DELAY_SLOT
target/sh4: Simplify 64-bit fp reg-reg move
target/sh4: Load/store Dr as 64-bit quantities
target/sh4: Merge DREG into fpr64 routines
target/sh4: Eliminate unused XREG macro
target/sh4: Hoist fp register bank selection
target/sh4: Pass DisasContext to fpr64 routines
target/sh4: Unify cpu_fregs into FREG
target/sh4: Hoist register bank selection
linux-user/sh4: Clean env->flags on signal boundaries
linux-user/sh4: Notice gUSA regions during signal delivery
...
* remotes/jnsnow/tags/ide-pull-request:
tests/ahci-test: Be mean with RAM
ahci: split public and private interface
ahci: Isolate public AHCI interface
ahci: add ahci_get_num_ports
# gpg: Signature made Tue 18 Jul 2017 16:39:33 BST
# gpg: using RSA key 0xF487EF185872D723
# gpg: Good signature from "Juan Quintela <[email protected]>"
# gpg: aka "Juan Quintela <[email protected]>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723
* remotes/juanquintela/tags/migration/20170718:
migration: check global caps for validity
migration: provide migrate_cap_add()
migration: provide migrate_caps_check()
migration: remove check against colo support
migration: check global params for validity
migration: provide migrate_params_apply()
migration: introduce migrate_params_check()
migration: export capabilities to props
migration: export parameters to props
qdev: provide DEFINE_PROP_INT64()
migration/rdma: Send error during cancelling
migration/rdma: Safely convert control types
migration/rdma: Allow cancelling while waiting for wrid
migration/rdma: fix qemu_rdma_block_for_wrid error paths
migration: Close file on failed migration load
migration/rdma: Fix race on source
Peter Maydell [Wed, 19 Jul 2017 09:48:31 +0000 (10:48 +0100)]
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Block layer patches
# gpg: Signature made Tue 18 Jul 2017 14:29:59 BST
# gpg: using RSA key 0x7F09B272C88F2FD6
# gpg: Good signature from "Kevin Wolf <[email protected]>"
# Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6
* remotes/kevin/tags/for-upstream: (21 commits)
qemu-img: Check for backing image if specified during create
blockdev: move BDRV_O_NO_BACKING option forward
block/vvfat: Fix compiler warning with gcc 7
vvfat: initialize memory after allocating it
vvfat: correctly parse non-ASCII short and long file names
vvfat: add a constant for bootsector name
vvfat: add constants for special values of name[0]
qemu-iotests: Test unplug of -device without drive
qemu-iotests: Test 'info block'
scsi-disk: bdrv_attach_dev() for empty CD-ROM
ide: bdrv_attach_dev() for empty CD-ROM
block: List anonymous device BBs in query-block
block/qapi: Use blk_all_next() for query-block
block: Make blk_all_next() public
block/qapi: Add qdev device name to query-block
block: Make blk_get_attached_dev_id() public
block/vpc.c: Handle write failures in get_image_offset()
block/vmdk: Report failures in vmdk_read_cid()
block: remove timer canceling in throttle_config()
block: add clock_type field to ThrottleGroup
...
This patch add a hmac speed benchmark, it helps us to
measure the performance by using "make check-speed" or
using "./tests/benchmark-crypto-hmac" directly.
This patch add a hash speed benchmark, it helps us to
measure the performance by using "make check-speed" or
using "./tests/benchmark-crypto-hash" directly.
Now we have two qcrypto backends, libiary-backend and afalg-backend,
but which one is faster? This patch add a cipher speed benchmark, it
helps us to measure the performance by using "make check-speed" or
using "./tests/benchmark-crypto-cipher" directly.
crypto: introduce some common functions for af_alg backend
The AF_ALG socket family is the userspace interface for linux
crypto API, this patch adds af_alg family support and some common
functions for af_alg backend. It'll be used by afalg-backend crypto
latter.
Signed-off-by: Longpeng(Mike) <[email protected]>
Maintainer: modified to report an error if AF_ALG is requested
but cannot be supported
Peter Maydell [Wed, 19 Jul 2017 08:11:38 +0000 (09:11 +0100)]
Merge remote-tracking branch 'remotes/berrange/tags/pull-qio-2017-07-18-1' into staging
Merge I/O 2017/07/18 v1
# gpg: Signature made Tue 18 Jul 2017 11:31:53 BST
# gpg: using RSA key 0xBE86EBB415104FDF
# gpg: Good signature from "Daniel P. Berrange <[email protected]>"
# gpg: aka "Daniel P. Berrange <[email protected]>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF
target/alpha: Merge several flag bytes into ENV->FLAGS
The flags are arranged such that we can manipulate them either
a whole, or as individual bytes. The computation within
cpu_get_tb_cpu_state is now reduced to a single load and mask.
This enforces proper alignment and makes the register update
more natural. Note that there is a more serious bug fix for
fmov {DX}Rn,@(R0,Rn) to use a store instead of a load.
linux-user/sh4: Clean env->flags on signal boundaries
If a signal is delivered during the execution of a delay slot,
or a gUSA region, clear those bits from the environment so that
the signal handler does not start in that same state.
Cleaning the bits on signal return is paranoid good sense.
linux-user/sh4: Notice gUSA regions during signal delivery
We translate gUSA regions atomically in a parallel context.
But in a serial context a gUSA region may be interrupted.
In that case, restart the region as the kernel would.
For many of the sequences produced by gcc or glibc,
we can translate these as host atomic operations.
Which saves the need to acquire the exclusive lock.
For uniprocessors, SH4 uses optimistic restartable atomic sequences.
Upon an interrupt, a real kernel would simply notice magic values in
the registers and reset the PC to the start of the sequence.
For QEMU, we cannot do this in quite the same way. Instead, we notice
the normal start of such a sequence (mov #-x,r15), and start a new TB
that can be executed under cpu_exec_step_atomic.
Since that the T bit of the SR register is mapped using a TGC global,
it's better to return the value through TCG than writing it directly. It
allows to declare the helpers with the flag TCG_CALL_NO_WG.
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