]> Git Repo - qemu.git/history - target/riscv
works with less than base ISA qemu-system-riscv32 -M virt -bios none -kernel output...
[qemu.git] / target / riscv /
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector mask...
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector floatin...
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector fix...
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector integer...
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector integer...
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vx instructions
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vector load...
2022-09-07 Yueh-Ting (eop)... target/riscv: rvv: Add mask agnostic for vv instructions
2022-09-07 Alexey Baturotarget/riscv: Fix typo and restore Pointer Masking...
2022-09-07 Weiwei Litarget/riscv: Simplify the check in hmode to reuse...
2022-09-07 Weiwei Litarget/riscv: Fix checks in hmode/hmode32
2022-09-07 Weiwei Litarget/riscv: Add check for csrs existed with U extension
2022-09-07 Weiwei Litarget/riscv: Fix checkpatch warning may triggered...
2022-09-07 Weiwei Litarget/riscv: H extension depends on I extension
2022-09-07 Weiwei Litarget/riscv: Add check for supported privilege mode...
2022-09-07 Weiwei Litarget/riscv: move zmmul out of the experimental properties
2022-09-07 Frédéric Pétrottarget/riscv: fix shifts shamt value for rv128c
2022-09-07 Anup Pateltarget/riscv: Force disable extensions if priv spec...
2022-09-07 Anup Pateltarget/riscv: Update [m|h]tinst CSR in riscv_cpu_do_int...
2022-09-06 Stefan HajnocziMerge tag 'samuel-thibault' of https://people.debian...
2022-09-06 Stefan HajnocziMerge tag 'pull-tcg-20220906' of https://gitlab.com...
2022-09-06 Richard Hendersontarget/riscv: Make translator stop before the end of...
2022-09-06 Richard Hendersontarget/riscv: Add MAX_INSN_LEN and insn_len
2022-09-06 Richard Hendersonaccel/tcg: Add pc and host_pc params to gen_intermediat...
2022-09-02 Stefan HajnocziMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2022-09-01 Paolo Bonzinimeson: remove dead code
2022-08-03 Richard HendersonMerge tag 'linux-user-for-7.1-pull-request' of https...
2022-07-29 Richard HendersonMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2022-07-28 Richard HendersonMerge tag 'pull-ppc-20220728' of https://gitlab.com...
2022-07-28 Richard HendersonMerge tag 'pull-riscv-to-apply-20220728' of github...
2022-07-27 Palmer DabbeltRISC-V: Allow both Zmmul and M
2022-07-04 Richard HendersonMerge tag 'kraxel-20220704-pull-request' of https:...
2022-07-03 Richard HendersonMerge tag 'pull-riscv-to-apply-20220703-1' of github...
2022-07-03 Anup Pateltarget/riscv: Update default priority table for local...
2022-07-03 Anup Pateltarget/riscv: Remove CSRs that set/clear an IMSIC inter...
2022-07-03 Anup Pateltarget/riscv: Set minumum priv spec version for mcounti...
2022-07-03 Anup Pateltarget/riscv: Don't force update priv spec version...
2022-07-03 Alistair Francistarget/riscv: Ibex: Support priv version 1.11
2022-07-03 Alistair Francistarget/riscv: Fixup MSECCFG minimum priv check
2022-07-03 Atish Patratarget/riscv: Support mcycle/minstret write operation
2022-07-03 Atish Patratarget/riscv: Add support for hpmcounters/hpmevents
2022-07-03 Atish Patratarget/riscv: Implement mcountinhibit CSR
2022-07-03 Atish Patratarget/riscv: pmu: Make number of counters configurable
2022-07-03 Atish Patratarget/riscv: pmu: Rename the counters extension to pmu
2022-07-03 Atish Patratarget/riscv: Implement PMU CSR predicate function...
2022-07-03 Atish Patratarget/riscv: Fix PMU CSR predicate function
2022-07-03 Nicolas Pitretarget/riscv/pmp: guard against PMP ranges with a negat...
2022-07-03 Richard Hendersontarget/riscv: Minimize the calls to decode_save_opc
2022-07-03 Richard Hendersontarget/riscv: Remove generate_exception_mtval
2022-07-03 Richard Hendersontarget/riscv: Set env->bins in gen_exception_illegal
2022-07-03 Víctor Colombotarget/riscv: Remove condition guarding register zero...
2022-06-28 Richard HendersonMerge tag 'for_upstream' of git://git.kernel.org/pub...
2022-06-28 Richard HendersonMerge tag 'pull-semi-20220628' of https://gitlab.com...
2022-06-27 Richard Hendersonsemihosting: Split out common-semi-target.h
2022-06-27 Richard Hendersonsemihosting: Return void from do_common_semihosting
2022-06-11 Richard HendersonMerge tag 'for_upstream' of git://git.kernel.org/pub...
2022-06-10 Richard HendersonMerge tag 'pull-riscv-to-apply-20220610' of github...
2022-06-09 Alistair Francistarget/riscv: trans_rvv: Avoid assert for RV32 and e64
2022-06-09 Alistair Francistarget/riscv: Don't expose the CPU properties on names...
2022-06-09 eopXDtarget/riscv: rvv: Add option 'rvv_ta_all_1s' to enable...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector permuta...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector mask...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector reducti...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector floatin...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector fix...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector integer...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector integer...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector integer...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vx, vvm, vxm...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vector load...
2022-06-09 eopXDtarget/riscv: rvv: Add tail agnostic for vv instructions
2022-06-09 eopXDtarget/riscv: rvv: Early exit when vstart >= vl
2022-06-09 eopXDtarget/riscv: rvv: Rename ambiguous esz
2022-06-09 eopXDtarget/riscv: rvv: Prune redundant access_type paramete...
2022-06-09 eopXDtarget/riscv: rvv: Prune redundant ESZ, DSZ parameter...
2022-06-09 Frédéric Pétrottarget/riscv/debug.c: keep experimental rv128 support...
2022-06-09 Andrew Brestickertarget/riscv: Wake on VS-level external interrupts
2022-06-09 Weiwei Litarget/riscv: add support for zmmul extension v0.1
2022-05-25 Richard HendersonMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2022-05-25 Richard HendersonMerge tag 'pull-aspeed-20220525' of https://github...
2022-05-25 Richard HendersonMerge tag 'linux-user-for-7.1-pull-request' of https...
2022-05-24 Richard HendersonMerge tag 'pull-riscv-to-apply-20220525' of github...
2022-05-24 Hongren (Zenithal... target/riscv: add zicsr/zifencei to isa_string
2022-05-24 Anup Pateltarget/riscv: Set [m|s]tval for both illegal and virtua...
2022-05-24 Anup Pateltarget/riscv: Fix hstatus.GVA bit setting for traps...
2022-05-24 Anup Pateltarget/riscv: Fix csr number based privilege checking
2022-05-24 Frank Changtarget/riscv: Fix typo of mimpid cpu option
2022-05-24 Weiwei Litarget/riscv: check 'I' and 'E' after checking 'G'...
2022-05-24 Tsukasa OItarget/riscv: Move/refactor ISA extension checks
2022-05-24 Tsukasa OItarget/riscv: FP extension requirements
2022-05-24 Tsukasa OItarget/riscv: Change "G" expansion
2022-05-24 Tsukasa OItarget/riscv: Disable "G" by default
2022-05-24 Tsukasa OItarget/riscv: Fix coding style on "G" expansion
2022-05-24 Tsukasa OItarget/riscv: Add short-isa-string option
2022-05-23 Tsukasa OItarget/riscv: Move Zhinx* extensions on ISA string
2022-05-23 eopXDtarget/riscv: rvv: Fix early exit condition for whole...
2022-05-23 Dylan Reidtarget/riscv: Fix VS mode hypervisor CSR access
2022-05-18 Richard HendersonMerge tag 'artist-cursor-fix-final-pull-request' of...
2022-05-15 Richard HendersonMerge tag 'or1k-pull-request-20220515' of https://githu...
2022-05-11 Richard HendersonMerge tag 'pull-misc-2022-05-11' of git://repo.or.cz...
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