]> Git Repo - qemu.git/commit
projects / qemu.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: d644e5e) | patch
target/riscv: add zicsr/zifencei to isa_string
authorHongren (Zenithal) Zheng <[email protected]>
Wed, 18 May 2022 12:46:58 +0000 (20:46 +0800)
committerAlistair Francis <[email protected]>
Tue, 24 May 2022 00:38:50 +0000 (10:38 +1000)
commit5160bacc0638088a7cb0180d2be3d8c2c8a21831
treef4ba73b24ec68d81f9fb05bbedca7b15d39352c2tree | snapshot
parentd644e5e44ff627d6b4da73a65795f60335ba4cb9commit | diff
target/riscv: add zicsr/zifencei to isa_string

Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.

Signed-off-by: Hongren (Zenithal) Zheng <[email protected]>
Tested-by: Jiatai He <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-Id: <YoTqwpfrodveJ7CR@Sun>
Signed-off-by: Alistair Francis <[email protected]>
target/riscv/cpu.c diff | blob | blame | history
Empty description
This page took 0.022413 seconds and 4 git commands to generate.