]> Git Repo - qemu.git/history - target/riscv/insn_trans
target/riscv: Enable privileged spec version 1.12
[qemu.git] / target / riscv / insn_trans /
2022-04-20 Richard HendersonMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2022-04-06 Marc-André LureauReplace config-time define HOST_WORDS_BIGENDIAN
2022-04-02 Peter MaydellMerge tag 'pull-request-2022-04-01' of https://gitlab...
2022-04-01 Peter MaydellMerge tag 'pull-target-arm-20220401' of https://git...
2022-04-01 Peter MaydellMerge tag 'pull-riscv-to-apply-20220401' of github...
2022-03-31 Yueh-Ting (eop)... target/riscv: rvv: Add missing early exit condition...
2022-03-08 Peter MaydellMerge remote-tracking branch 'remotes/mst/tags/for_upst...
2022-03-04 Peter MaydellMerge remote-tracking branch 'remotes/kraxel/tags/kraxe...
2022-03-04 Peter MaydellMerge remote-tracking branch 'remotes/nvme/tags/nvme...
2022-03-04 Peter MaydellMerge remote-tracking branch 'remotes/rth-gitlab/tags...
2022-03-03 Peter MaydellMerge remote-tracking branch 'remotes/alistair/tags...
2022-03-03 Weiwei Litarget/riscv: add support for zhinx/zhinxmin
2022-03-03 Weiwei Litarget/riscv: add support for zdinx
2022-03-03 Weiwei Litarget/riscv: add support for zfinx
2022-03-03 Philipp Tomsichtarget/riscv: fix inverted checks for ext_zb[abcs]
2022-02-23 Peter MaydellMerge remote-tracking branch 'remotes/berrange-gitlab...
2022-02-21 Peter MaydellMerge remote-tracking branch 'remotes/bonzini-gitlab...
2022-02-16 Peter MaydellMerge remote-tracking branch 'remotes/alistair/tags...
2022-02-16 Weiwei Litarget/riscv: add support for svinval extension
2022-02-16 Philipp Tomsichtarget/riscv: Add XVentanaCondOps custom extension
2022-02-16 Philipp Tomsichtarget/riscv: access cfg structure through DisasContext
2022-02-16 Philipp Tomsichtarget/riscv: access configuration through cfg_ptr...
2022-02-02 Peter MaydellMerge remote-tracking branch 'remotes/hdeller/tags...
2022-01-21 Peter MaydellMerge remote-tracking branch 'remotes/alistair/tags...
2022-01-21 LIU Zhiweitarget/riscv: Adjust scalar reg in vector with XLEN
2022-01-21 LIU Zhiweitarget/riscv: Calculate address according to XLEN
2022-01-21 LIU Zhiweitarget/riscv: Adjust csr write mask with XLEN
2022-01-21 LIU Zhiweitarget/riscv: Sign extend pc for different XLEN
2022-01-21 LIU Zhiweitarget/riscv: Sign extend link reg for jal and jalr
2022-01-21 LIU Zhiweitarget/riscv: Don't save pc when exception return
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for narrowing...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for widening...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for single...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for scalar...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve32f support for configura...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for narrowing...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for widening...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for single...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for scalar...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for vsmul...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for vmulh...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for load...
2022-01-21 Frank Changtarget/riscv: rvv-1.0: Add Zve64f support for configura...
2022-01-12 Cédric Le GoaterMerge tag 'qemu-slof-20220110' of github.com:aik/qemu...
2022-01-11 Peter MaydellMerge remote-tracking branch 'remotes/philmd/tags/sdmmc...
2022-01-11 Peter MaydellMerge remote-tracking branch 'remotes/mst/tags/for_upst...
2022-01-08 Richard HendersonMerge tag 'bsd-user-arm-pull-request' of gitlab.com...
2022-01-08 Richard HendersonMerge tag 'pull-riscv-to-apply-20220108' of github...
2022-01-08 Frédéric Pétrottarget/riscv: modification of the trans_csrxx for 128...
2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit M extension
2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit arithmetic instructions
2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit shift instructions
2022-01-08 Frédéric Pétrottarget/riscv: support for 128-bit U-type instructions
2022-01-08 Frédéric Pétrottarget/riscv: accessors to registers upper part and...
2022-01-08 Frédéric Pétrottarget/riscv: moving some insns close to similar insns
2022-01-08 Frédéric Pétrottarget/riscv: separation of bitwise logic and arithmeti...
2022-01-08 Frédéric Pétrotexec/memop: Adding signedness to quad definitions
2022-01-08 Frank Changtarget/riscv: rvv-1.0: Call the correct RVF/RVD check...
2022-01-08 Frank Changtarget/riscv: rvv-1.0: Call the correct RVF/RVD check...
2022-01-08 Frank Changtarget/riscv: rvv-1.0: Call the correct RVF/RVD check...
2021-12-20 Richard HendersonMerge tag 'pull-user-20211220' of https://gitlab.com...
2021-12-20 Richard HendersonMerge tag 'pull-riscv-to-apply-20211220-1' of github...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: Add ELEN checks for widening...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: update opivv_vadc_check() comment
2021-12-20 Frank Changtarget/riscv: rvv-1.0: rename vmandnot.mm and vmornot...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: add vector unit-stride mask...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: add vsetivli instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point reciprocal estima...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point reciprocal square...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: trigger illegal instruction...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: implement vstart CSR
2021-12-20 Frank Changtarget/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing floating-point/integer...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point/integer...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point/integer type...
2021-12-20 Frank Changtarget/riscv: introduce floating-point rounding mode...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove integer extract instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove vmford.vv and vmford.vf
2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove widening saturating scale...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width scaling shift instr...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point reductio...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width floating-point...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing fixed-point clip instr...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point slide instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: mask-register logical instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer comparison instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width saturating add...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing integer right shift...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer add-with-carry/subtract...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width bit shift instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width averaging add and...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer extension instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: whole register move instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point scalar move instr...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point move instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer scalar move instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: register gather instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: allow load element with sign...
2021-12-20 Frank Changtarget/riscv: rvv-1.0: iota instruction
2021-12-20 Frank Changtarget/riscv: rvv-1.0: set-X-first mask bit instructions
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