int maskimm = (1 << (OP2 + 1)) - 1;
TCGv_i32 tmp = tcg_temp_new_i32();
-
- if (shiftimm) {
- tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
- } else {
- tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
- }
-
- switch (maskimm) {
- case 0xff:
- tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp);
- break;
-
- case 0xffff:
- tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp);
- break;
-
- default:
- tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
- break;
- }
+ tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
+ tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
tcg_temp_free(tmp);
}
break;