static inline void pxa2xx_rtc_int_update(PXA2xxState *s)
{
- qemu_set_irq(s->pic[PXA2XX_PIC_RTCALARM], !!(s->rtsr & 0x2553));
+ qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
}
static void pxa2xx_rtc_hzupdate(PXA2xxState *s)
s->rtc_swal1 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal1_tick, s);
s->rtc_swal2 = qemu_new_timer(rt_clock, pxa2xx_rtc_swal2_tick, s);
s->rtc_pi = qemu_new_timer(rt_clock, pxa2xx_rtc_pi_tick, s);
+
+ s->rtc_irq = qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM);
}
static void pxa2xx_rtc_save(QEMUFile *f, void *opaque)
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
- s->dma = pxa27x_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
+ s->dma = pxa27x_dma_init(0x40000000,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
- pxa27x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0],
- s->pic[PXA27X_PIC_OST_4_11]);
+ pxa27x_timer_init(0x40a00000, s->pic);
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
exit(1);
}
s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
- s->pic[PXA2XX_PIC_MMC], s->dma);
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
for (i = 0; pxa270_serial[i].io_base; i ++)
if (serial_hds[i])
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa270_serial[i].io_base, 2,
- s->pic[pxa270_serial[i].irqn], 14857000/16,
- serial_hds[i], 1, 1);
+ qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
+ 14857000 / 16, serial_hds[i], 1, 1);
#else
serial_mm_init(pxa270_serial[i].io_base, 2,
- s->pic[pxa270_serial[i].irqn], 14857000/16,
- serial_hds[i], 1, 0);
+ qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
+ 14857000 / 16, serial_hds[i], 1, 0);
#endif
else
break;
if (serial_hds[i])
- s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
+ s->fir = pxa2xx_fir_init(0x40800000,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
s->dma, serial_hds[i]);
- s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
+ s->lcd = pxa2xx_lcdc_init(0x44000000,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
for (i = 0; pxa27x_ssp[i].io_base; i ++) {
DeviceState *dev;
dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
- s->pic[pxa27x_ssp[i].irqn]);
+ qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
}
if (usb_enabled) {
sysbus_create_simple("sysbus-ohci", 0x4c000000,
- s->pic[PXA2XX_PIC_USBH1]);
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
}
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
pxa2xx_rtc_load, s);
- s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
- s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
+ s->i2c[0] = pxa2xx_i2c_init(0x40301600,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
+ s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
- s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
+ s->i2s = pxa2xx_i2s_init(0x40400000,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma);
- s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
+ s->kp = pxa27x_keypad_init(0x41500000,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
/* GPIO1 resets the processor */
/* The handler can be overridden by board-specific code */
s->pic = pxa2xx_pic_init(0x40d00000, s->env);
- s->dma = pxa255_dma_init(0x40000000, s->pic[PXA2XX_PIC_DMA]);
+ s->dma = pxa255_dma_init(0x40000000,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
- pxa25x_timer_init(0x40a00000, &s->pic[PXA2XX_PIC_OST_0]);
+ pxa25x_timer_init(0x40a00000, s->pic);
s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
exit(1);
}
s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
- s->pic[PXA2XX_PIC_MMC], s->dma);
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
for (i = 0; pxa255_serial[i].io_base; i ++)
if (serial_hds[i]) {
#ifdef TARGET_WORDS_BIGENDIAN
serial_mm_init(pxa255_serial[i].io_base, 2,
- s->pic[pxa255_serial[i].irqn], 14745600/16,
- serial_hds[i], 1, 1);
+ qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
+ 14745600 / 16, serial_hds[i], 1, 1);
#else
serial_mm_init(pxa255_serial[i].io_base, 2,
- s->pic[pxa255_serial[i].irqn], 14745600/16,
- serial_hds[i], 1, 0);
+ qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
+ 14745600 / 16, serial_hds[i], 1, 0);
#endif
} else {
break;
}
if (serial_hds[i])
- s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
+ s->fir = pxa2xx_fir_init(0x40800000,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
s->dma, serial_hds[i]);
- s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
+ s->lcd = pxa2xx_lcdc_init(0x44000000,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
for (i = 0; pxa255_ssp[i].io_base; i ++) {
DeviceState *dev;
dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
- s->pic[pxa255_ssp[i].irqn]);
+ qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
}
if (usb_enabled) {
sysbus_create_simple("sysbus-ohci", 0x4c000000,
- s->pic[PXA2XX_PIC_USBH1]);
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
}
s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
register_savevm(NULL, "pxa2xx_rtc", 0, 0, pxa2xx_rtc_save,
pxa2xx_rtc_load, s);
- s->i2c[0] = pxa2xx_i2c_init(0x40301600, s->pic[PXA2XX_PIC_I2C], 0xffff);
- s->i2c[1] = pxa2xx_i2c_init(0x40f00100, s->pic[PXA2XX_PIC_PWRI2C], 0xff);
+ s->i2c[0] = pxa2xx_i2c_init(0x40301600,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
+ s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
- s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
+ s->i2s = pxa2xx_i2s_init(0x40400000,
+ qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma);
/* GPIO1 resets the processor */
/* The handler can be overridden by board-specific code */
#include "hw.h"
#include "pxa.h"
+#include "sysbus.h"
#define ICIP 0x00 /* Interrupt Controller IRQ Pending register */
#define ICMR 0x04 /* Interrupt Controller Mask register */
#define PXA2XX_PIC_SRCS 40
typedef struct {
+ SysBusDevice busdev;
CPUState *cpu_env;
uint32_t int_enabled[2];
uint32_t int_pending[2];
pxa2xx_pic_mem_write,
};
-static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
+static int pxa2xx_pic_post_load(void *opaque, int version_id)
{
- PXA2xxPICState *s = (PXA2xxPICState *) opaque;
- int i;
-
- for (i = 0; i < 2; i ++)
- qemu_put_be32s(f, &s->int_enabled[i]);
- for (i = 0; i < 2; i ++)
- qemu_put_be32s(f, &s->int_pending[i]);
- for (i = 0; i < 2; i ++)
- qemu_put_be32s(f, &s->is_fiq[i]);
- qemu_put_be32s(f, &s->int_idle);
- for (i = 0; i < PXA2XX_PIC_SRCS; i ++)
- qemu_put_be32s(f, &s->priority[i]);
-}
-
-static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id)
-{
- PXA2xxPICState *s = (PXA2xxPICState *) opaque;
- int i;
-
- for (i = 0; i < 2; i ++)
- qemu_get_be32s(f, &s->int_enabled[i]);
- for (i = 0; i < 2; i ++)
- qemu_get_be32s(f, &s->int_pending[i]);
- for (i = 0; i < 2; i ++)
- qemu_get_be32s(f, &s->is_fiq[i]);
- qemu_get_be32s(f, &s->int_idle);
- for (i = 0; i < PXA2XX_PIC_SRCS; i ++)
- qemu_get_be32s(f, &s->priority[i]);
-
pxa2xx_pic_update(opaque);
return 0;
}
-qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
+DeviceState *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
{
- PXA2xxPICState *s;
+ DeviceState *dev = qdev_create(NULL, "pxa2xx_pic");
int iomemtype;
- qemu_irq *qi;
-
- s = (PXA2xxPICState *)
- qemu_mallocz(sizeof(PXA2xxPICState));
- if (!s)
- return NULL;
+ PXA2xxPICState *s = FROM_SYSBUS(PXA2xxPICState, sysbus_from_qdev(dev));
s->cpu_env = env;
s->is_fiq[0] = 0;
s->is_fiq[1] = 0;
- qi = qemu_allocate_irqs(pxa2xx_pic_set_irq, s, PXA2XX_PIC_SRCS);
+ qdev_init_nofail(dev);
+
+ qdev_init_gpio_in(dev, pxa2xx_pic_set_irq, PXA2XX_PIC_SRCS);
/* Enable IC memory-mapped registers access. */
iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn,
pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x00100000, iomemtype);
+ sysbus_init_mmio(sysbus_from_qdev(dev), 0x00100000, iomemtype);
/* Enable IC coprocessor access. */
cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
- register_savevm(NULL, "pxa2xx_pic", 0, 0, pxa2xx_pic_save,
- pxa2xx_pic_load, s);
+ return dev;
+}
+
+static VMStateDescription vmstate_pxa2xx_pic_regs = {
+ .name = "pxa2xx_pic",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .minimum_version_id_old = 0,
+ .post_load = pxa2xx_pic_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(int_enabled, PXA2xxPICState, 2),
+ VMSTATE_UINT32_ARRAY(int_pending, PXA2xxPICState, 2),
+ VMSTATE_UINT32_ARRAY(is_fiq, PXA2xxPICState, 2),
+ VMSTATE_UINT32(int_idle, PXA2xxPICState),
+ VMSTATE_UINT32_ARRAY(priority, PXA2xxPICState, PXA2XX_PIC_SRCS),
+ VMSTATE_END_OF_LIST(),
+ },
+};
- return qi;
+static int pxa2xx_pic_initfn(SysBusDevice *dev)
+{
+ return 0;
+}
+
+static SysBusDeviceInfo pxa2xx_pic_info = {
+ .init = pxa2xx_pic_initfn,
+ .qdev.name = "pxa2xx_pic",
+ .qdev.desc = "PXA2xx PIC",
+ .qdev.size = sizeof(PXA2xxPICState),
+ .qdev.vmsd = &vmstate_pxa2xx_pic_regs,
+};
+
+static void pxa2xx_pic_register(void)
+{
+ sysbus_register_withprop(&pxa2xx_pic_info);
}
+device_init(pxa2xx_pic_register);
projects / qemu.git / commitdiff