]> Git Repo - qemu.git/commitdiff
target/riscv: Add a virtualised MMU Mode
authorAlistair Francis <[email protected]>
Wed, 4 Nov 2020 04:43:23 +0000 (20:43 -0800)
committerAlistair Francis <[email protected]>
Mon, 9 Nov 2020 23:08:45 +0000 (15:08 -0800)
Add a new MMU mode that includes the current virt mode.

Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: 4b301bc0ea36da962fc1605371b65019ac3073df.1604464950[email protected]

target/riscv/cpu-param.h
target/riscv/cpu.h
target/riscv/cpu_helper.c

index 664fc1d371a4fd098bfea4e325e9278db90e7874..80eb615f93f49f3870559c691dfcb5a795610c82 100644 (file)
 # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
 #endif
 #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
-#define NB_MMU_MODES 4
+/*
+ * The current MMU Modes are:
+ *  - U mode 0b000
+ *  - S mode 0b001
+ *  - M mode 0b011
+ *  - U mode HLV/HLVX/HSV 0b100
+ *  - S mode HLV/HLVX/HSV 0b101
+ *  - M mode HLV/HLVX/HSV 0b111
+ */
+#define NB_MMU_MODES 8
 
 #endif
index 87b68affa85f2a3c8bdd51ea81b6e693fb5e194f..5d8e54c426b7baa64b3dc66b6e240928e63f108c 100644 (file)
@@ -363,7 +363,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
 
-#define TB_FLAGS_MMU_MASK   3
+#define TB_FLAGS_MMU_MASK   7
+#define TB_FLAGS_PRIV_MMU_MASK                3
+#define TB_FLAGS_PRIV_HYP_ACCESS_MASK   (1 << 2)
 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
 
 typedef CPURISCVState CPUArchState;
index 3eb3a034dbdd8955ee172ab82865e4b8d7f7318a..9dfa7af401a80579fbd8f7fe8c33262b7d9a098c 100644 (file)
@@ -323,7 +323,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      * (riscv_cpu_do_interrupt) is correct */
     MemTxResult res;
     MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
-    int mode = mmu_idx;
+    int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
     bool use_background = false;
 
     /*
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