]> Git Repo - qemu.git/commitdiff
tcg: Change flush_icache_range arguments to uintptr_t
authorRichard Henderson <[email protected]>
Tue, 20 Aug 2013 21:22:50 +0000 (14:22 -0700)
committerRichard Henderson <[email protected]>
Mon, 2 Sep 2013 16:08:29 +0000 (09:08 -0700)
Reviewed-by: Aurelien Jarno <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
tcg/aarch64/tcg-target.h
tcg/arm/tcg-target.h
tcg/hppa/tcg-target.h
tcg/i386/tcg-target.h
tcg/ia64/tcg-target.h
tcg/mips/tcg-target.h
tcg/s390/tcg-target.h
tcg/sparc/tcg-target.h
tcg/tcg.c
tcg/tci/tcg-target.h

index 26ee28b12cda6d1065db4b9c244748f8532441ef..d3a1bc24371a35ede7a59ac23991953497b4df10 100644 (file)
@@ -96,8 +96,7 @@ enum {
     TCG_AREG0 = TCG_REG_X19,
 };
 
-static inline void flush_icache_range(tcg_target_ulong start,
-                                      tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
     __builtin___clear_cache((char *)start, (char *)stop);
 }
index ed48092431c25d98310ab01be87b8b2aaaf875c3..9482bfa993ee59e0a067071ee9927c752d5c49aa 100644 (file)
@@ -92,15 +92,14 @@ enum {
     TCG_AREG0 = TCG_REG_R6,
 };
 
-static inline void flush_icache_range(tcg_target_ulong start,
-                                      tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
 #if QEMU_GNUC_PREREQ(4, 1)
     __builtin___clear_cache((char *) start, (char *) stop);
 #else
-    register unsigned long _beg __asm ("a1") = start;
-    register unsigned long _end __asm ("a2") = stop;
-    register unsigned long _flg __asm ("a3") = 0;
+    register uintptr_t _beg __asm("a1") = start;
+    register uintptr_t _end __asm("a2") = stop;
+    register uintptr_t _flg __asm("a3") = 0;
     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 #endif
 }
index 0f6f2ff35d110b00f9d949e10e079a4ae5cc42ea..be5895f847fa2b580cb70d388e56e7dffcfe2891 100644 (file)
@@ -111,8 +111,7 @@ typedef enum {
 #define TCG_AREG0 TCG_REG_R17
 
 
-static inline void flush_icache_range(tcg_target_ulong start,
-                                      tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
     start &= ~31;
     while (start <= stop) {
index b7d1a555bbfa954bfc396b7e5d9bf91f8b155aca..1f6c7eb8a595ac9ac3a3a7141503afb7e0e5609c 100644 (file)
@@ -139,8 +139,7 @@ typedef enum {
 # define TCG_AREG0 TCG_REG_EBP
 #endif
 
-static inline void flush_icache_range(tcg_target_ulong start,
-                                      tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
 }
 
index ee6b2c8a245a790c6ec13becdf4824d7a5b5bc3c..4330c9cdd3c3d4daa78ac79d7d7d9a0f0c48896f 100644 (file)
@@ -162,8 +162,7 @@ typedef enum {
 
 #define TCG_AREG0 TCG_REG_R7
 
-static inline void flush_icache_range(tcg_target_ulong start,
-                                      tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
     start = start & ~(32UL - 1UL);
     stop = (stop + (32UL - 1UL)) & ~(32UL - 1UL);
index 7ef79e087960beb2e83e472f90472ec909debf2d..a820328093dda11da1da893b0b6fe3fcf6fd4d7c 100644 (file)
@@ -127,8 +127,7 @@ typedef enum {
 #include <sys/cachectl.h>
 #endif
 
-static inline void flush_icache_range(tcg_target_ulong start,
-                                      tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
     cacheflush ((void *)start, stop-start, ICACHE);
 }
index b02f170d8327f47c3de8a64866de7e64a8a3d510..6142fb26a23f15b235f1e7d5febf0e99e92487fd 100644 (file)
@@ -114,8 +114,7 @@ enum {
     TCG_AREG0 = TCG_REG_R10,
 };
 
-static inline void flush_icache_range(tcg_target_ulong start,
-                                      tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
 }
 
index 1a696bc97a55a661ab1f074863f0c3bd7b7dda53..c0d3abcc7dafd3dcb491d22e59999350b78950ea 100644 (file)
@@ -142,16 +142,12 @@ typedef enum {
 
 #define TCG_AREG0 TCG_REG_I0
 
-static inline void flush_icache_range(tcg_target_ulong start,
-                                      tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
-    unsigned long p;
-
-    p = start & ~(8UL - 1UL);
-    stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
-
-    for (; p < stop; p += 8)
+    uintptr_t p;
+    for (p = start & -8; p < (stop + 7) & -8; p += 8) {
         __asm__ __volatile__("flush\t%0" : : "r" (p));
+    }
 }
 
 #endif
index 541a4425172ca35fd8243e0711ed57778760ca96..65cffcae8ab3e7a6e0fe390bc7277eb5665810ad 100644 (file)
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -293,8 +293,7 @@ void tcg_prologue_init(TCGContext *s)
     s->code_buf = s->code_gen_prologue;
     s->code_ptr = s->code_buf;
     tcg_target_qemu_prologue(s);
-    flush_icache_range((tcg_target_ulong)s->code_buf,
-                       (tcg_target_ulong)s->code_ptr);
+    flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
 
 #ifdef DEBUG_DISAS
     if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
@@ -2415,8 +2414,7 @@ int tcg_gen_code(TCGContext *s, uint8_t *gen_code_buf)
     tcg_gen_code_common(s, gen_code_buf, -1);
 
     /* flush instruction cache */
-    flush_icache_range((tcg_target_ulong)gen_code_buf,
-                       (tcg_target_ulong)s->code_ptr);
+    flush_icache_range((uintptr_t)gen_code_buf, (uintptr_t)s->code_ptr);
 
     return s->code_ptr -  gen_code_buf;
 }
index ff12b4b9c77c7ad22f1d58190a894d997a23ccdb..e284972d92fac1527698b680f070d11c864024b2 100644 (file)
@@ -172,8 +172,7 @@ void tci_disas(uint8_t opc);
 tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
 #define tcg_qemu_tb_exec tcg_qemu_tb_exec
 
-static inline void flush_icache_range(tcg_target_ulong start,
-                                      tcg_target_ulong stop)
+static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 {
 }
 
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