addr_trans, len, flags);
}
+/* ACPI 1.0b: 6.4.2.2 DMA Format/6.4.2.2.1 ASL Macro for DMA Descriptor */
+Aml *aml_dma(AmlDmaType typ, AmlDmaBusMaster bm, AmlTransferSize sz,
+ uint8_t channel)
+{
+ Aml *var = aml_alloc();
+ uint8_t flags = sz | bm << 2 | typ << 5;
+
+ assert(channel < 8);
+ build_append_byte(var->buf, 0x2A); /* Byte 0: DMA Descriptor */
+ build_append_byte(var->buf, 1U << channel); /* Byte 1: _DMA - DmaChannel */
+ build_append_byte(var->buf, flags); /* Byte 2 */
+ return var;
+}
+
/* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefSleep */
Aml *aml_sleep(uint64_t msec)
{
};
typedef struct Aml Aml;
+typedef enum {
+ AML_COMPATIBILITY = 0,
+ AML_TYPEA = 1,
+ AML_TYPEB = 2,
+ AML_TYPEF = 3,
+} AmlDmaType;
+
+typedef enum {
+ AML_NOTBUSMASTER = 0,
+ AML_BUSMASTER = 1,
+} AmlDmaBusMaster;
+
+typedef enum {
+ AML_TRANSFER8 = 0,
+ AML_TRANSFER8_16 = 1,
+ AML_TRANSFER16 = 2,
+} AmlTransferSize;
+
typedef enum {
AML_DECODE10 = 0,
AML_DECODE16 = 1,
uint64_t addr_gran, uint64_t addr_min,
uint64_t addr_max, uint64_t addr_trans,
uint64_t len);
+Aml *aml_dma(AmlDmaType typ, AmlDmaBusMaster bm, AmlTransferSize sz,
+ uint8_t channel);
Aml *aml_sleep(uint64_t msec);
/* Block AML object primitives */