/**
* LM32CPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A LatticeMico32 CPU model.
CPUClass parent_class;
/*< public >*/
+ DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} LM32CPUClass;
memset(env, 0, offsetof(CPULM32State, breakpoints));
}
+static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+ LM32CPU *cpu = LM32_CPU(dev);
+ LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
+
+ cpu_reset(CPU(cpu));
+
+ qemu_init_vcpu(&cpu->env);
+
+ lcc->parent_realize(dev, errp);
+}
+
static void lm32_cpu_initfn(Object *obj)
{
LM32CPU *cpu = LM32_CPU(obj);
cpu_exec_init(env);
env->flags = 0;
-
- cpu_reset(CPU(cpu));
}
static void lm32_cpu_class_init(ObjectClass *oc, void *data)
{
LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ lcc->parent_realize = dc->realize;
+ dc->realize = lm32_cpu_realizefn;
lcc->parent_reset = cc->reset;
cc->reset = lm32_cpu_reset;
env->num_wps = def->num_watchpoints;
env->cfg = cfg_by_def(def);
- qemu_init_vcpu(env);
-
if (tcg_enabled() && !tcg_initialized) {
tcg_initialized = 1;
lm32_translate_init();
}
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
return cpu;
}