void check_interrupts(CPUXtensaState *env)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int minlevel = xtensa_get_cintlevel(env);
uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
int level;
void cpu_loop(CPUXtensaState *env)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
target_siginfo_t info;
abi_ulong ret;
int trapnr;
CPUXtensaState env;
};
-static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env)
-{
- return container_of(env, XtensaCPU, env);
-}
-
#define ENV_OFFSET offsetof(XtensaCPU, env)
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
+typedef CPUXtensaState CPUArchState;
+typedef XtensaCPU ArchCPU;
+
+#include "exec/cpu-all.h"
+
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
*pc = env->pc;
*cs_base = 0;
}
}
-typedef CPUXtensaState CPUArchState;
-typedef XtensaCPU ArchCPU;
-
-#include "exec/cpu-all.h"
-
#endif
static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
uint32_t dbreakc)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
uint32_t mask = dbreakc | ~DBREAKC_MASK;
set_dbreak(env, i, env->sregs[DBREAKA + i], v);
} else {
if (env->cpu_watchpoint[i]) {
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
env->cpu_watchpoint[i] = NULL;
void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
cs->exception_index = excp;
if (excp == EXCP_YIELD) {
void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
{
- CPUState *cpu;
+ CPUState *cpu = env_cpu(env);
env->pc = pc;
env->sregs[PS] = (env->sregs[PS] & ~PS_INTLEVEL) |
qemu_mutex_unlock_iothread();
if (env->pending_irq_level) {
- cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
+ cpu_loop_exit(cpu);
return;
}
- cpu = CPU(xtensa_env_get_cpu(env));
cpu->halted = 1;
HELPER(exception)(env, EXCP_HLT);
}
(env->config->level_mask[level] &
env->sregs[INTSET] &
env->sregs[INTENABLE])) {
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
if (level > 1) {
env->sregs[EPC1 + level - 1] = env->pc;
void xtensa_runstall(CPUXtensaState *env, bool runstall)
{
- CPUState *cpu = CPU(xtensa_env_get_cpu(env));
+ CPUState *cpu = env_cpu(env);
env->runstall = runstall;
cpu->halted = runstall;
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
{
- XtensaCPU *cpu = xtensa_env_get_cpu(env);
-
v = (v & 0xffffff00) | 0x1;
if (v != env->sregs[RASID]) {
env->sregs[RASID] = v;
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
}
unsigned wi, unsigned ei,
uint32_t vpn, uint32_t pte)
{
- XtensaCPU *cpu = xtensa_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = env_cpu(env);
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
if (entry->variable && entry->asid) {
- tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
+ tlb_flush_page(env_cpu(env), entry->vaddr);
entry->asid = 0;
}
}
static bool get_pte(CPUXtensaState *env, uint32_t vaddr, uint32_t *pte)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t paddr;
uint32_t page_size;
unsigned access;
void HELPER(wsr_mpuenb)(CPUXtensaState *env, uint32_t v)
{
- XtensaCPU *cpu = xtensa_env_get_cpu(env);
-
v &= (2u << (env->config->n_mpu_fg_segments - 1)) - 1;
if (v != env->sregs[MPUENB]) {
env->sregs[MPUENB] = v;
- tlb_flush(CPU(cpu));
+ tlb_flush(env_cpu(env));
}
}
env->mpu_fg[segment].vaddr = v & -env->config->mpu_align;
env->mpu_fg[segment].attr = p & XTENSA_MPU_ATTR_MASK;
env->sregs[MPUENB] = deposit32(env->sregs[MPUENB], segment, 1, v);
- tlb_flush(CPU(xtensa_env_get_cpu(env)));
+ tlb_flush(env_cpu(env));
}
}
void HELPER(simcall)(CPUXtensaState *env)
{
- CPUState *cs = CPU(xtensa_env_get_cpu(env));
+ CPUState *cs = env_cpu(env);
uint32_t *regs = env->regs;
switch (regs[2]) {