return s->apicbase;
}
+void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
+{
+ APICState *s = env->apic_state;
+ s->tpr = (val & 0x0f) << 4;
+}
+
+uint8_t cpu_get_apic_tpr(CPUX86State *env)
+{
+ APICState *s = env->apic_state;
+ return s->tpr >> 4;
+}
+
/* return -1 if no bit is set */
static int get_highest_priority_int(uint32_t *tab)
{
void *opaque;
} CPUX86State;
-#ifndef IN_OP_I386
-void cpu_x86_outb(CPUX86State *env, int addr, int val);
-void cpu_x86_outw(CPUX86State *env, int addr, int val);
-void cpu_x86_outl(CPUX86State *env, int addr, int val);
-int cpu_x86_inb(CPUX86State *env, int addr);
-int cpu_x86_inw(CPUX86State *env, int addr);
-int cpu_x86_inl(CPUX86State *env, int addr);
-#endif
-
CPUX86State *cpu_x86_init(void);
int cpu_x86_exec(CPUX86State *s);
void cpu_x86_close(CPUX86State *s);
void cpu_set_apic_base(CPUX86State *env, uint64_t val);
uint64_t cpu_get_apic_base(CPUX86State *env);
+void cpu_set_apic_tpr(CPUX86State *env, uint8_t val);
+#ifndef NO_CPU_IO_DEFS
+uint8_t cpu_get_apic_tpr(CPUX86State *env);
+#endif
/* will be suppressed */
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
case 2:
case 3:
case 4:
+ case 8:
if (b & 2) {
gen_op_mov_TN_reg[ot][0][rm]();
gen_op_movl_crN_T0(reg);
gen_jmp_im(s->pc - s->cs_base);
gen_eob(s);
} else {
- gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg]));
+ if (reg == 8)
+ gen_op_movtl_T0_cr8();
+ else
+ gen_op_movtl_T0_env(offsetof(CPUX86State,cr[reg]));
gen_op_mov_reg_T0[ot][rm]();
}
break;
- /* XXX: add CR8 for x86_64 */
default:
goto illegal_op;
}