switch_v7m_security_state(env, dest & 1);
env->thumb = 1;
env->regs[15] = dest & ~1;
+ arm_rebuild_hflags(env);
}
void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest)
switch_v7m_security_state(env, 0);
env->thumb = 1;
env->regs[15] = dest;
+ arm_rebuild_hflags(env);
}
static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool threadmode,
env->regs[14] = lr;
env->regs[15] = addr & 0xfffffffe;
env->thumb = addr & 1;
+ arm_rebuild_hflags(env);
}
static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr,
/* Otherwise, we have a successful exception exit. */
arm_clear_exclusive(env);
+ arm_rebuild_hflags(env);
qemu_log_mask(CPU_LOG_INT, "...successful exception return\n");
}
xpsr_write(env, 0, XPSR_IT);
env->thumb = newpc & 1;
env->regs[15] = newpc & ~1;
+ arm_rebuild_hflags(env);
qemu_log_mask(CPU_LOG_INT, "...function return successful\n");
return true;
switch_v7m_security_state(env, true);
xpsr_write(env, 0, XPSR_IT);
env->regs[15] += 4;
+ arm_rebuild_hflags(env);
return true;
gen_invep:
static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
{
- TCGv_i32 addr, reg;
+ TCGv_i32 addr, reg, el;
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
return false;
gen_helper_v7m_msr(cpu_env, addr, reg);
tcg_temp_free_i32(addr);
tcg_temp_free_i32(reg);
+ el = tcg_const_i32(s->current_el);
+ gen_helper_rebuild_hflags_m32(cpu_env, el);
+ tcg_temp_free_i32(el);
gen_lookup_tb(s);
return true;
}