sparc64: add macros to deal with softint and timer interrupt

Signed-off-by: Igor V. Kovalenko <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>

diff --git a/hw/sun4u.c b/hw/sun4u.c
index 9d46f088153e84dd22d5578c8f08f1748a0e945d..029e3edc5f1b5c95b41e81e5dff85cea28319a23 100644 (file)
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -73,7 +73,6 @@
 
 #define MAX_PILS 16
 
-#define TICK_INT_DIS         0x8000000000000000ULL
 #define TICK_MAX             0x7fffffffffffffffULL
 
 struct hwdef {

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 1fe4d0f1e4fdfd161b1b7a3cfa0ecc6a8ad7593a..0f0e38cf2c745d036b8e94cb5af450f8243dd9ad 100644 (file)
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -394,6 +394,8 @@ typedef struct CPUSPARCState {
     uint64_t fprs;
     uint64_t tick_cmpr, stick_cmpr;
     void *tick, *stick;
+#define TICK_NPT_MASK        0x8000000000000000ULL
+#define TICK_INT_DIS         0x8000000000000000ULL
     uint64_t gsr;
     uint32_t gl; // UA2005
     /* UA 2005 hyperprivileged registers */
@@ -402,6 +404,8 @@ typedef struct CPUSPARCState {
     uint32_t softint;
 #define SOFTINT_TIMER   1
 #define SOFTINT_STIMER  (1 << 16)
+#define SOFTINT_INTRMASK (0xFFFE)
+#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
 #endif
     sparc_def_t *def;
 } CPUSPARCState;