SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).

Main purpose of this is to delete
       *physical = address & 0x1fffffff;
at target-sh4/helper.c:449, using new mmio rule introduced by #5849
This masking is a nice trick to realize P4/A7 duality of SH registers.
But, IMHO, it is logically wrong.

Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have
one more address called A7 which is usually P4 address with upper 3bits masked.
This is an address only appears in TLB's physical address part.

Current code use trick writing drivers as if they are really in A7
(that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7.

Signed-off-by: Takashi YOSHII <[email protected]>
Signed-off-by: Andrzej Zaborowski <[email protected]>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/hw/sh.h b/hw/sh.h
index 116441a7dd369154757c7ec0ff844caa1cc40282..5e3c22bbb96ce1bbfe857f91b6ed14d6480ff144 100644 (file)
--- a/hw/sh.h
+++ b/hw/sh.h
@@ -4,6 +4,9 @@
 
 #include "sh_intc.h"
 
+#define A7ADDR(x) ((x) & 0x1fffffff)
+#define P4ADDR(x) ((x) | 0xe0000000)
+
 /* sh7750.c */
 struct SH7750State;
 

diff --git a/hw/sh7750.c b/hw/sh7750.c
index afdb9f5bcbd0830af057d2b3e6c90a1d230b7197..af86f0e990e10a07d47907c7b6a992632e9f578f 100644 (file)
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -683,10 +683,16 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
                                              sh7750_mem_write, s);
     cpu_register_physical_memory_offset(0x1f000000, 0x1000,
                                         sh7750_io_memory, 0x1f000000);
+    cpu_register_physical_memory_offset(0xff000000, 0x1000,
+                                        sh7750_io_memory, 0x1f000000);
     cpu_register_physical_memory_offset(0x1f800000, 0x1000,
                                         sh7750_io_memory, 0x1f800000);
+    cpu_register_physical_memory_offset(0xff800000, 0x1000,
+                                        sh7750_io_memory, 0x1f800000);
     cpu_register_physical_memory_offset(0x1fc00000, 0x1000,
                                         sh7750_io_memory, 0x1fc00000);
+    cpu_register_physical_memory_offset(0xffc00000, 0x1000,
+                                        sh7750_io_memory, 0x1fc00000);
 
     sh7750_mm_cache_and_tlb = cpu_register_io_memory(0,
                                                     sh7750_mmct_read,

diff --git a/hw/sh_intc.c b/hw/sh_intc.c
index b62633d31224dc67e02a5c563ed015db1584fbed..7d738d16ca294c93167ca6cba893abbcbefbd803 100644 (file)
--- a/hw/sh_intc.c
+++ b/hw/sh_intc.c
@@ -307,9 +307,12 @@ struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
 static void sh_intc_register(struct intc_desc *desc, 
                             unsigned long address)
 {
-    if (address)
-        cpu_register_physical_memory_offset(INTC_A7(address), 4,
+    if (address) {
+        cpu_register_physical_memory_offset(P4ADDR(address), 4,
                                             desc->iomemtype, INTC_A7(address));
+        cpu_register_physical_memory_offset(A7ADDR(address), 4,
+                                            desc->iomemtype, INTC_A7(address));
+    }
 }
 
 static void sh_intc_register_source(struct intc_desc *desc,

diff --git a/hw/sh_serial.c b/hw/sh_serial.c
index 8397739de982b2b651e38c5501443f86b435a26e..843031e8a5cc0d52ed34905f9a73266a9ee6ae9c 100644 (file)
--- a/hw/sh_serial.c
+++ b/hw/sh_serial.c
@@ -399,7 +399,8 @@ void sh_serial_init (target_phys_addr_t base, int feat,
 
     s_io_memory = cpu_register_io_memory(0, sh_serial_readfn,
                                         sh_serial_writefn, s);
-    cpu_register_physical_memory(base, 0x28, s_io_memory);
+    cpu_register_physical_memory(P4ADDR(base), 0x28, s_io_memory);
+    cpu_register_physical_memory(A7ADDR(base), 0x28, s_io_memory);
 
     s->chr = chr;
 

diff --git a/hw/sh_timer.c b/hw/sh_timer.c
index 4557a8354c07025fd1c8e5bb0817bf78fadf5b97..c5c45f50d2e511986bf7887277dfd73b71d6c225 100644 (file)
--- a/hw/sh_timer.c
+++ b/hw/sh_timer.c
@@ -320,6 +320,7 @@ void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
                                    ch2_irq0); /* ch2_irq1 not supported */
     iomemtype = cpu_register_io_memory(0, tmu012_readfn,
                                        tmu012_writefn, s);
-    cpu_register_physical_memory(base, 0x00001000, iomemtype);
+    cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
+    cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype);
     /* ??? Save/restore.  */
 }

diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index f077462f7d7fdf65935442aef3c2105972138e68..c2cc4325e718c83ada867c9c8aa0a22d1aa4d3ab 100644 (file)
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -439,19 +439,7 @@ int get_physical_address(CPUState * env, target_ulong * physical,
        if (address >= 0x80000000 && address < 0xc0000000) {
            /* Mask upper 3 bits for P1 and P2 areas */
            *physical = address & 0x1fffffff;
-        } else if (address >= 0xfd000000 && address < 0xfe000000) {
-            /* PCI memory space */
-            *physical = address;
-       } else if (address >= 0xfc000000) {
-           /*
-            * Mask upper 3 bits for control registers in P4 area,
-            * to unify access to control registers via P0-P3 area.
-            * The addresses for cache store queue, TLB address array
-            * are not masked.
-            */
-       *physical = address & 0x1fffffff;
        } else {
-           /* access to cache store queue, or TLB address array. */
            *physical = address;
        }
        *prot = PAGE_READ | PAGE_WRITE;