Merge branch 'tcg-next' of git://github.com/rth7680/qemu

* 'tcg-next' of git://github.com/rth7680/qemu: (29 commits)
  tcg-i386: Make use of zero-extended memory helper routines
  tcg: Introduce zero and sign-extended versions of load helpers
  exec: Split softmmu_defs.h
  target: Include softmmu_exec.h where forgotten
  exec: Rename USUFFIX to LSUFFIX
  tcg-i386: Don't perform GETPC adjustment in TCG code
  exec: Reorganize the GETRA/GETPC macros
  configure: Allow x32 as a host
  tcg-i386: Adjust tcg_out_tlb_load for x32
  tcg-i386: Use intptr_t appropriately
  tcg: Fix jit debug for x32
  tcg: Use appropriate types in tcg_reg_alloc_call
  tcg: Change tcg_out_ld/st offset to intptr_t
  tcg: Change tcg_gen_exit_tb argument to uintptr_t
  tcg: Use uintptr_t in TCGHelperInfo
  tcg: Change relocation offsets to intptr_t
  tcg: Change memory offsets to intptr_t
  tcg: Change frame pointer offsets to intptr_t
  tcg: Define TCG_ptr properly
  tcg: Define TCG_TYPE_PTR properly
  ...

diff --cc target-ppc/mmu_helper.c
Simple merge

diff --cc target-ppc/translate.c
Simple merge

diff --cc tcg/mips/tcg-target.c
Simple merge

diff --cc tcg/mips/tcg-target.h
index 76ee83195ea51c49c9250d631c2a65e9fb83eae3,a820328093dda11da1da893b0b6fe3fcf6fd4d7c..c37252269f804a30b7522d3f2fb564d19d25fff2
--- 1/tcg/mips/tcg-target.h
--- 2/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@@ -110,15 -89,30 +110,17 @@@ extern bool use_mips32r2_instructions
  #define TCG_TARGET_HAS_eqv_i32          0
  #define TCG_TARGET_HAS_nand_i32         0
  #define TCG_TARGET_HAS_muls2_i32        1
+ #define TCG_TARGET_HAS_muluh_i32        1
+ #define TCG_TARGET_HAS_mulsh_i32        1
  
 -/* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */
 -#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
 -    defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
 -    defined(_MIPS_ARCH_MIPS4)
 -#define TCG_TARGET_HAS_movcond_i32      1
 -#else
 -#define TCG_TARGET_HAS_movcond_i32      0
 -#endif
 -
 -/* optional instructions only implemented on MIPS32R2 */
 -#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
 -#define TCG_TARGET_HAS_bswap16_i32      1
 -#define TCG_TARGET_HAS_bswap32_i32      1
 -#define TCG_TARGET_HAS_rot_i32          1
 -#define TCG_TARGET_HAS_deposit_i32      1
 -#else
 -#define TCG_TARGET_HAS_bswap16_i32      0
 -#define TCG_TARGET_HAS_bswap32_i32      0
 -#define TCG_TARGET_HAS_rot_i32          0
 -#define TCG_TARGET_HAS_deposit_i32      0
 -#endif
 +/* optional instructions detected at runtime */
 +#define TCG_TARGET_HAS_movcond_i32      use_movnz_instructions
 +#define TCG_TARGET_HAS_bswap16_i32      use_mips32r2_instructions
 +#define TCG_TARGET_HAS_bswap32_i32      use_mips32r2_instructions
 +#define TCG_TARGET_HAS_deposit_i32      use_mips32r2_instructions
 +#define TCG_TARGET_HAS_ext8s_i32        use_mips32r2_instructions
 +#define TCG_TARGET_HAS_ext16s_i32       use_mips32r2_instructions
 +#define TCG_TARGET_HAS_rot_i32          use_mips32r2_instructions
  
  /* optional instructions automatically implemented */
  #define TCG_TARGET_HAS_neg_i32          0 /* sub  rd, zero, rt   */