Write zeros to high bits of y, based on patch by Vince Weaver

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5196 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 3d7d958b762a6990b9e9ec9bdb8d93de5c8f3a17..fc28aebef4e70172f26f77fc5fe41b5742b18e50 100644 (file)
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -709,7 +709,8 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
     tcg_gen_andi_tl(r_temp, cpu_cc_src, 0x1);
     tcg_gen_shli_tl(r_temp, r_temp, 31);
     tcg_gen_shri_tl(cpu_tmp0, cpu_y, 1);
-    tcg_gen_or_tl(cpu_y, cpu_tmp0, r_temp);
+    tcg_gen_or_tl(cpu_tmp0, cpu_tmp0, r_temp);
+    tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
 
     // b1 = N ^ V;
     gen_mov_reg_N(cpu_tmp0, cpu_psr);
@@ -3195,7 +3196,8 @@ static void disas_sparc_insn(DisasContext * dc)
                         {
                             switch(rd) {
                             case 0: /* wry */
-                                tcg_gen_xor_tl(cpu_y, cpu_src1, cpu_src2);
+                                tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2);
+                                tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
                                 break;
 #ifndef TARGET_SPARC64
                             case 0x01 ... 0x0f: /* undefined in the