#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
/* Basic Machine Configuration */
-struct sysib_111 {
- uint32_t res1[8];
+typedef struct SysIB_111 {
+ uint8_t res1[32];
uint8_t manuf[16];
uint8_t type[4];
uint8_t res2[12];
uint8_t model[16];
uint8_t sequence[16];
uint8_t plant[4];
- uint8_t res3[156];
-};
+ uint8_t res3[3996];
+} SysIB_111;
+QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
/* Basic Machine CPU */
-struct sysib_121 {
- uint32_t res1[80];
+typedef struct SysIB_121 {
+ uint8_t res1[80];
uint8_t sequence[16];
uint8_t plant[4];
uint8_t res2[2];
uint16_t cpu_addr;
- uint8_t res3[152];
-};
+ uint8_t res3[3992];
+} SysIB_121;
+QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
/* Basic Machine CPUs */
-struct sysib_122 {
+typedef struct SysIB_122 {
uint8_t res1[32];
uint32_t capability;
uint16_t total_cpus;
uint16_t standby_cpus;
uint16_t reserved_cpus;
uint16_t adjustments[2026];
-};
+} SysIB_122;
+QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
/* LPAR CPU */
-struct sysib_221 {
- uint32_t res1[80];
+typedef struct SysIB_221 {
+ uint8_t res1[80];
uint8_t sequence[16];
uint8_t plant[4];
uint16_t cpu_id;
uint16_t cpu_addr;
- uint8_t res3[152];
-};
+ uint8_t res3[3992];
+} SysIB_221;
+QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
/* LPAR CPUs */
-struct sysib_222 {
- uint32_t res1[32];
+typedef struct SysIB_222 {
+ uint8_t res1[32];
uint16_t lpar_num;
uint8_t res2;
uint8_t lcpuc;
uint8_t res3[16];
uint16_t dedicated_cpus;
uint16_t shared_cpus;
- uint8_t res4[180];
-};
+ uint8_t res4[4020];
+} SysIB_222;
+QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
/* VM CPUs */
-struct sysib_322 {
+typedef struct SysIB_322 {
uint8_t res1[31];
uint8_t count;
struct {
} vm[8];
uint8_t res4[1504];
uint8_t ext_names[8][256];
-};
+} SysIB_322;
+QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
/* MMU defines */
#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
case STSI_LEVEL_1:
if ((sel1 == 1) && (sel2 == 1)) {
/* Basic Machine Configuration */
- struct sysib_111 sysib;
+ SysIB_111 sysib;
char type[5] = {};
memset(&sysib, 0, sizeof(sysib));
cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
} else if ((sel1 == 2) && (sel2 == 1)) {
/* Basic Machine CPU */
- struct sysib_121 sysib;
+ SysIB_121 sysib;
memset(&sysib, 0, sizeof(sysib));
/* XXX make different for different CPUs? */
cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
} else if ((sel1 == 2) && (sel2 == 2)) {
/* Basic Machine CPUs */
- struct sysib_122 sysib;
+ SysIB_122 sysib;
memset(&sysib, 0, sizeof(sysib));
stl_p(&sysib.capability, 0x443afc29);
{
if ((sel1 == 2) && (sel2 == 1)) {
/* LPAR CPU */
- struct sysib_221 sysib;
+ SysIB_221 sysib;
memset(&sysib, 0, sizeof(sysib));
/* XXX make different for different CPUs? */
cpu_physical_memory_write(a0, &sysib, sizeof(sysib));
} else if ((sel1 == 2) && (sel2 == 2)) {
/* LPAR CPUs */
- struct sysib_222 sysib;
+ SysIB_222 sysib;
memset(&sysib, 0, sizeof(sysib));
stw_p(&sysib.lpar_num, 0);
{
if ((sel1 == 2) && (sel2 == 2)) {
/* VM CPUs */
- struct sysib_322 sysib;
+ SysIB_322 sysib;
memset(&sysib, 0, sizeof(sysib));
sysib.count = 1;