PCI: Mask writes to RO bits in the command reg of PCI config space

The Command register in the PCI config space has some read-only bits.
Any writes to those bits should be masked out.

Signed-off-by: Amit Shah <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6092 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/hw/pci.c b/hw/pci.c
index b95c79440cbc1803a0b1008fab721ca675e4c141..8252d21b9552020119a6b91977e864ddf8785f29 100644 (file)
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -417,6 +417,9 @@ void pci_default_write_config(PCIDevice *d,
         if (can_write) {
             /* Mask out writes to reserved bits in registers */
             switch (addr) {
+           case 0x05:
+                val &= ~PCI_COMMAND_RESERVED_MASK_HI;
+                break;
             case 0x06:
                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
                 break;

diff --git a/hw/pci.h b/hw/pci.h
index 95905db1ec0dad24f962a0f786aab61f6f71e590..3b1caf5ca81ba53c073f9eae14d526cd23f8c2c3 100644 (file)
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -69,6 +69,11 @@ typedef struct PCIIORegion {
 
 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 
+/* Bits in the PCI Command Register (PCI 2.3 spec) */
+#define PCI_COMMAND_RESERVED   0xf800
+
+#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
+
 struct PCIDevice {
     /* PCI config space */
     uint8_t config[256];