INSN_LDRD_REG = 0x000000d0,
INSN_STRD_IMM = 0x004000f0,
INSN_STRD_REG = 0x000000f0,
+
+ INSN_DMB_ISH = 0x5bf07ff5,
+ INSN_DMB_MCR = 0xba0f07ee,
+
} ARMInsn;
#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
}
}
+static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+ if (use_armv7_instructions) {
+ tcg_out32(s, INSN_DMB_ISH);
+ } else if (use_armv6_instructions) {
+ tcg_out32(s, INSN_DMB_MCR);
+ }
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
break;
+ case INDEX_op_mb:
+ tcg_out_mb(s, args[0]);
+ break;
+
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_call: /* Always emitted via tcg_out_call. */
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
+ { INDEX_op_mb, { } },
{ -1 },
};