Catch more MIPS FPU cornercases, fix addr.ps and mulr.ps instructions.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2841 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 9a0ffee9af26d762ceb7359e0e7fe036abce2efe..9092ffc39d12d4e6872e6742745c00b451eeb9d9 100644 (file)
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -975,13 +975,25 @@ FLOAT_OP(name, d)         \
 {                         \
     set_float_exception_flags(0, &env->fp_status);            \
     FDT2 = float64_ ## name (FDT0, FDT1, &env->fp_status);    \
-    update_fcr31();       \
+    update_fcr31();                                           \
+    if (GET_FP_CAUSE(env->fcr31) & FP_INVALID)                \
+        FDT2 = 0x7ff7ffffffffffffULL;                         \
+    else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) {       \
+        if ((env->fcr31 & 0x3) == 0)                          \
+            FDT2 &= 0x8000000000000000ULL;                    \
+    }                     \
 }                         \
 FLOAT_OP(name, s)         \
 {                         \
     set_float_exception_flags(0, &env->fp_status);            \
     FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
-    update_fcr31();       \
+    update_fcr31();                                           \
+    if (GET_FP_CAUSE(env->fcr31) & FP_INVALID)                \
+        FST2 = 0x7fbfffff;                                    \
+    else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) {       \
+        if ((env->fcr31 & 0x3) == 0)                          \
+            FST2 &= 0x80000000ULL;                            \
+    }                     \
 }                         \
 FLOAT_OP(name, ps)        \
 {                         \
@@ -989,6 +1001,15 @@ FLOAT_OP(name, ps)        \
     FST2 = float32_ ## name (FST0, FST1, &env->fp_status);    \
     FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fp_status); \
     update_fcr31();       \
+    if (GET_FP_CAUSE(env->fcr31) & FP_INVALID) {              \
+        FST2 = 0x7fbfffff;                                    \
+        FSTH2 = 0x7fbfffff;                                   \
+    } else if (GET_FP_CAUSE(env->fcr31) & FP_UNDERFLOW) {     \
+        if ((env->fcr31 & 0x3) == 0) {                        \
+            FST2 &= 0x80000000ULL;                            \
+            FSTH2 &= 0x80000000ULL;                           \
+        }                 \
+    }                     \
 }
 FLOAT_BINOP(add)
 FLOAT_BINOP(sub)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 03f802a2724e8402a810c708abca177f28d5e132..5b497d0fdaeded895880300a855bc504598ad345 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5074,10 +5074,10 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
         break;
     case FOP(24, 22):
         gen_op_cp1_64bitmode();
-        GEN_LOAD_FREG_FTN(WT0, fs);
-        GEN_LOAD_FREG_FTN(WTH0, fs);
-        GEN_LOAD_FREG_FTN(WT1, ft);
-        GEN_LOAD_FREG_FTN(WTH1, ft);
+        GEN_LOAD_FREG_FTN(WT0, ft);
+        GEN_LOAD_FREG_FTN(WTH0, ft);
+        GEN_LOAD_FREG_FTN(WT1, fs);
+        GEN_LOAD_FREG_FTN(WTH1, fs);
         gen_op_float_addr_ps();
         GEN_STORE_FTN_FREG(fd, WT2);
         GEN_STORE_FTN_FREG(fd, WTH2);
@@ -5085,10 +5085,10 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, int ft,
         break;
     case FOP(26, 22):
         gen_op_cp1_64bitmode();
-        GEN_LOAD_FREG_FTN(WT0, fs);
-        GEN_LOAD_FREG_FTN(WTH0, fs);
-        GEN_LOAD_FREG_FTN(WT1, ft);
-        GEN_LOAD_FREG_FTN(WTH1, ft);
+        GEN_LOAD_FREG_FTN(WT0, ft);
+        GEN_LOAD_FREG_FTN(WTH0, ft);
+        GEN_LOAD_FREG_FTN(WT1, fs);
+        GEN_LOAD_FREG_FTN(WTH1, fs);
         gen_op_float_mulr_ps();
         GEN_STORE_FTN_FREG(fd, WT2);
         GEN_STORE_FTN_FREG(fd, WTH2);