target-mips: Fix incorrect code and test for INSV

Content of register rs should be shifted for pos before applying a mask.
This change contains both fix for the instruction and to the existing test.

Signed-off-by: Petar Jovanovic <[email protected]>
Reviewed-by: Eric Johnson <[email protected]>
Signed-off-by: Aurelien Jarno <[email protected]>

diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index e7949c22c0b3bcc97ae756c09557e6578be18374..fda5f0460bd59b5d13ce6b1775e8ddd2b6ffb6fc 100644 (file)
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs,  \
                                                                 \
     filter = ((int32_t)0x01 << size) - 1;                       \
     filter = filter << pos;                                     \
-    temprs = rs & filter;                                       \
+    temprs = (rs << pos) & filter;                              \
     temprt = rt & ~filter;                                      \
     temp = temprs | temprt;                                     \
                                                                 \

diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c
index 7e3b0476064dc6f93e659b7c11d3be2ba15dfd2f..243b00733d4f6886674c92c78ba87102c0643859 100644 (file)
--- a/tests/tcg/mips/mips32-dsp/insv.c
+++ b/tests/tcg/mips/mips32-dsp/insv.c
@@ -10,7 +10,7 @@ int main()
     dsp    = 0x305;
     rt     = 0x12345678;
     rs     = 0x87654321;
-    result = 0x12345338;
+    result = 0x12345438;
     __asm
         ("wrdsp %2, 0x03\n\t"
          "insv  %0, %1\n\t"