target-arm: Move block cache ops to new cp15 framework

Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.

Signed-off-by: Peter Maydell <[email protected]>

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9b28f6b59771a62cc7745fda056bb47937903b24..10d46356e5e0a20c9ed67c0bda140adc470a3928 100644 (file)
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -810,6 +810,19 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
     /* We never have a a block transfer operation in progress */
     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+    /* The cache ops themselves: these all NOP for QEMU */
+    { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
+      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
+      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
+      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
+      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
+      .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+    { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
+      .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
     REGINFO_SENTINEL
 };
 

diff --git a/target-arm/translate.c b/target-arm/translate.c
index f4e9435c4b2f4bd4254d37e903494eb4751b23c0..fcdc9d31665b6892a169ed14ac842510bf3a1657 100644 (file)
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2451,12 +2451,7 @@ static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
        return 1;
 
     if ((insn & (1 << 25)) == 0) {
-        if (insn & (1 << 20)) {
-            /* mrrc */
-            return 1;
-        }
-        /* mcrr.  Used for block cache operations, so implement as no-op.  */
-        return 0;
+        return 1;
     }
     if ((insn & (1 << 4)) == 0) {
         /* cdp */