cpu: flush TB cache when loading VMState

Flushing TB cache is required because TBs key in the cache may match
different code which existed in the previous state.

Signed-off-by: Pavel Dovgalyuk <[email protected]>
Signed-off-by: Maria Klimushenkova <[email protected]>
Message-Id: <20180110134846.12940.99993.stgit@pasha-VirtualBox>
[Add comment suggested by Peter Maydell. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Signed-off-by: Pavel Dovgalyuk <[email protected]>

diff --git a/exec.c b/exec.c
index 9f4f4501a8a1b3c07b474d5ba33a2d8ff2db105c..d28fc0cd3d9fd2e0a77aaa27d0343202d46bef88 100644 (file)
--- a/exec.c
+++ b/exec.c
@@ -623,6 +623,13 @@ static int cpu_common_post_load(void *opaque, int version_id)
     cpu->interrupt_request &= ~0x01;
     tlb_flush(cpu);
 
+    /* loadvm has just updated the content of RAM, bypassing the
+     * usual mechanisms that ensure we flush TBs for writes to
+     * memory we've translated code from. So we must flush all TBs,
+     * which will now be stale.
+     */
+    tb_flush(cpu);
+
     return 0;
 }