target-arm: Fix REVIDR reset value

According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let
REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57.

Signed-off-by: Sergey Fedorov <[email protected]>
Message-id: 1433321048[email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index ed5a6441bbc80a8c11ff4b892871f6fdf9f96961..c80381da89b3432c50347af044b7e8fc70d99d17 100644 (file)
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -127,6 +127,7 @@ typedef struct ARMCPU {
      * prefix means a constant register.
      */
     uint32_t midr;
      * prefix means a constant register.
      */
     uint32_t midr;

+    uint32_t revidr;

     uint32_t reset_fpsid;
     uint32_t mvfr0;
     uint32_t mvfr1;
     uint32_t reset_fpsid;
     uint32_t mvfr0;
     uint32_t mvfr1;

diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index dd6f9d86f9835bb250efcadf87ab56e9caf83125..63c8b1cfa9b54badc94f9fc9fe1474ae55d9186c 100644 (file)
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -110,6 +110,7 @@ static void aarch64_a57_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_CRC);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
     cpu->midr = 0x411fd070;
     set_feature(&cpu->env, ARM_FEATURE_CRC);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
     cpu->midr = 0x411fd070;

+    cpu->revidr = 0x00000000;

     cpu->reset_fpsid = 0x41034070;
     cpu->mvfr0 = 0x10110222;
     cpu->mvfr1 = 0x12111111;
     cpu->reset_fpsid = 0x41034070;
     cpu->mvfr0 = 0x10110222;
     cpu->mvfr1 = 0x12111111;


@@ -161,6 +162,7 @@ static void aarch64_a53_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_CRC);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
     cpu->midr = 0x410fd034;
     set_feature(&cpu->env, ARM_FEATURE_CRC);
     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
     cpu->midr = 0x410fd034;

+    cpu->revidr = 0x00000000;

     cpu->reset_fpsid = 0x41034070;
     cpu->mvfr0 = 0x10110222;
     cpu->mvfr1 = 0x12111111;
     cpu->reset_fpsid = 0x41034070;
     cpu->mvfr0 = 0x10110222;
     cpu->mvfr1 = 0x12111111;

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 611b0e7cdc4079f89e47d2a5819a1a46a95e9848..8053ad598b3dad7d39c1673b486e8c09737dc70d 100644 (file)
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3424,15 +3424,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         };
         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
         };
         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
             /* v8 MIDR -- the wildcard isn't necessary, and nor is the

-             * variable-MIDR TI925 behaviour. Instead we have a single
-             * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
+             * variable-MIDR TI925 behaviour.

              */
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
              */
             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,

-              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
+              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },

             REGINFO_SENTINEL
         };
         ARMCPRegInfo id_cp_reginfo[] = {
             REGINFO_SENTINEL
         };
         ARMCPRegInfo id_cp_reginfo[] = {