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(parent: 5da4a6a) | patch
target-xtensa: add special and user registers
authorMax Filippov <[email protected]>
Mon, 5 Sep 2011 23:55:33 +0000 (03:55 +0400)
committerBlue Swirl <[email protected]>
Sat, 10 Sep 2011 16:57:37 +0000 (16:57 +0000)
commit2af3da91839c04a5d73643b4eacce4cd93b9d428
treeb7351a28a6060aaf9f70d7688569f9fa74f74116tree | snapshot
parent5da4a6a8c5271234fdc2ab53b80cf7a23952849bcommit | diff
target-xtensa: add special and user registers

Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.

User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details.

Only registers mapped in sregnames or uregnames are considered valid.

Signed-off-by: Max Filippov <[email protected]>
Signed-off-by: Blue Swirl <[email protected]>
target-xtensa/cpu.h diff | blob | blame | history
target-xtensa/translate.c diff | blob | blame | history
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