]> Git Repo - qemu.git/commit
target/arm: Clear unused predicate bits for LD1RQ
authorRichard Henderson <[email protected]>
Mon, 8 Oct 2018 13:55:03 +0000 (14:55 +0100)
committerPeter Maydell <[email protected]>
Mon, 8 Oct 2018 13:55:03 +0000 (14:55 +0100)
commit2a99ab2b3545133961de034df27e24f4c22e3707
treed96c8650632b711d3043e7d398d9d93fda72ed3c
parentced3155141755ba244c988c72c4bde32cc819670
target/arm: Clear unused predicate bits for LD1RQ

The 16-byte load only uses 16 predicate bits.  But while
reusing the other load infrastructure, we find other bits
that are set and trigger an assert.  To avoid this and
retain the assert, zero-extend the predicate that we pass
to the LD1 helper.

Tested-by: Laurent Desnogues <[email protected]>
Reported-by: Laurent Desnogues <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: 20181005175350[email protected]
Signed-off-by: Peter Maydell <[email protected]>
target/arm/translate-sve.c
This page took 0.028307 seconds and 4 git commands to generate.