#include "qemu/log.h"
#include "qemu/bitops.h"
#include "exec/cpu_ldst.h"
+#include "exec/translator.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
+#include "exec/gen-icount.h"
#include "trace-tcg.h"
#include "exec/log.h"
+#define LOG_DIS(str, ...) \
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \
+ ## __VA_ARGS__)
-#define OPENRISC_DISAS
-
-#ifdef OPENRISC_DISAS
-# define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
-#else
-# define LOG_DIS(...) do { } while (0)
-#endif
+/* is_jmp field values */
+#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
+#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
+#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
typedef struct DisasContext {
- TranslationBlock *tb;
- target_ulong pc, ppc, npc;
- uint32_t tb_flags, synced_flags, flags;
- uint32_t is_jmp;
+ DisasContextBase base;
uint32_t mem_idx;
- int singlestep_enabled;
+ uint32_t tb_flags;
uint32_t delayed_branch;
} DisasContext;
-static TCGv_env cpu_env;
+/* Include the auto-generated decoder. */
+#include "decode.inc.c"
+
static TCGv cpu_sr;
static TCGv cpu_R[32];
+static TCGv cpu_R0;
static TCGv cpu_pc;
static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
-static TCGv cpu_npc;
static TCGv cpu_ppc;
-static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */
+static TCGv cpu_sr_f; /* bf/bnf, F flag taken */
+static TCGv cpu_sr_cy; /* carry (unsigned overflow) */
+static TCGv cpu_sr_ov; /* signed overflow */
+static TCGv cpu_lock_addr;
+static TCGv cpu_lock_value;
static TCGv_i32 fpcsr;
-static TCGv machi, maclo;
-static TCGv fpmaddhi, fpmaddlo;
-static TCGv_i32 env_flags;
-#include "exec/gen-icount.h"
+static TCGv_i64 cpu_mac; /* MACHI:MACLO */
+static TCGv_i32 cpu_dflag;
void openrisc_translate_init(void)
{
};
int i;
- cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
- tcg_ctx.tcg_env = cpu_env;
cpu_sr = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, sr), "sr");
- env_flags = tcg_global_mem_new_i32(cpu_env,
- offsetof(CPUOpenRISCState, flags),
- "flags");
+ cpu_dflag = tcg_global_mem_new_i32(cpu_env,
+ offsetof(CPUOpenRISCState, dflag),
+ "dflag");
cpu_pc = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, pc), "pc");
- cpu_npc = tcg_global_mem_new(cpu_env,
- offsetof(CPUOpenRISCState, npc), "npc");
cpu_ppc = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, ppc), "ppc");
jmp_pc = tcg_global_mem_new(cpu_env,
offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
- env_btaken = tcg_global_mem_new_i32(cpu_env,
- offsetof(CPUOpenRISCState, btaken),
- "btaken");
+ cpu_sr_f = tcg_global_mem_new(cpu_env,
+ offsetof(CPUOpenRISCState, sr_f), "sr_f");
+ cpu_sr_cy = tcg_global_mem_new(cpu_env,
+ offsetof(CPUOpenRISCState, sr_cy), "sr_cy");
+ cpu_sr_ov = tcg_global_mem_new(cpu_env,
+ offsetof(CPUOpenRISCState, sr_ov), "sr_ov");
+ cpu_lock_addr = tcg_global_mem_new(cpu_env,
+ offsetof(CPUOpenRISCState, lock_addr),
+ "lock_addr");
+ cpu_lock_value = tcg_global_mem_new(cpu_env,
+ offsetof(CPUOpenRISCState, lock_value),
+ "lock_value");
fpcsr = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUOpenRISCState, fpcsr),
"fpcsr");
- machi = tcg_global_mem_new(cpu_env,
- offsetof(CPUOpenRISCState, machi),
- "machi");
- maclo = tcg_global_mem_new(cpu_env,
- offsetof(CPUOpenRISCState, maclo),
- "maclo");
- fpmaddhi = tcg_global_mem_new(cpu_env,
- offsetof(CPUOpenRISCState, fpmaddhi),
- "fpmaddhi");
- fpmaddlo = tcg_global_mem_new(cpu_env,
- offsetof(CPUOpenRISCState, fpmaddlo),
- "fpmaddlo");
+ cpu_mac = tcg_global_mem_new_i64(cpu_env,
+ offsetof(CPUOpenRISCState, mac),
+ "mac");
for (i = 0; i < 32; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUOpenRISCState, gpr[i]),
+ offsetof(CPUOpenRISCState,
+ shadow_gpr[0][i]),
regnames[i]);
}
-}
-
-/* Writeback SR_F translation space to execution space. */
-static inline void wb_SR_F(void)
-{
- TCGLabel *label = gen_new_label();
- tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
- tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
- tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
- gen_set_label(label);
-}
-
-static inline int zero_extend(unsigned int val, int width)
-{
- return val & ((1 << width) - 1);
-}
-
-static inline int sign_extend(unsigned int val, int width)
-{
- int sval;
-
- /* LSL */
- val <<= TARGET_LONG_BITS - width;
- sval = val;
- /* ASR. */
- sval >>= TARGET_LONG_BITS - width;
- return sval;
-}
-
-static inline void gen_sync_flags(DisasContext *dc)
-{
- /* Sync the tb dependent flag between translate and runtime. */
- if (dc->tb_flags != dc->synced_flags) {
- tcg_gen_movi_tl(env_flags, dc->tb_flags);
- dc->synced_flags = dc->tb_flags;
- }
+ cpu_R0 = cpu_R[0];
}
static void gen_exception(DisasContext *dc, unsigned int excp)
static void gen_illegal_exception(DisasContext *dc)
{
- tcg_gen_movi_tl(cpu_pc, dc->pc);
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
gen_exception(dc, EXCP_ILLEGAL);
- dc->is_jmp = DISAS_UPDATE;
+ dc->base.is_jmp = DISAS_NORETURN;
}
/* not used yet, open it when we need or64. */
}
#endif*/
+/* We're about to write to REG. On the off-chance that the user is
+ writing to R0, re-instate the architectural register. */
+#define check_r0_write(reg) \
+ do { \
+ if (unlikely(reg == 0)) { \
+ cpu_R[0] = cpu_R0; \
+ } \
+ } while (0)
+
static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
{
- if (unlikely(dc->singlestep_enabled)) {
+ if (unlikely(dc->base.singlestep_enabled)) {
return false;
}
#ifndef CONFIG_USER_ONLY
- return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
+ return (dc->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
#else
return true;
#endif
if (use_goto_tb(dc, dest)) {
tcg_gen_movi_tl(cpu_pc, dest);
tcg_gen_goto_tb(n);
- tcg_gen_exit_tb((uintptr_t)dc->tb + n);
+ tcg_gen_exit_tb((uintptr_t)dc->base.tb + n);
} else {
tcg_gen_movi_tl(cpu_pc, dest);
- if (dc->singlestep_enabled) {
+ if (dc->base.singlestep_enabled) {
gen_exception(dc, EXCP_DEBUG);
}
tcg_gen_exit_tb(0);
}
}
-static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
+static void gen_ove_cy(DisasContext *dc)
{
- target_ulong tmp_pc;
- /* N26, 26bits imm */
- tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
+ if (dc->tb_flags & SR_OVE) {
+ gen_helper_ove_cy(cpu_env);
+ }
+}
- switch (op0) {
- case 0x00: /* l.j */
- tcg_gen_movi_tl(jmp_pc, tmp_pc);
- break;
- case 0x01: /* l.jal */
- tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
- tcg_gen_movi_tl(jmp_pc, tmp_pc);
- break;
- case 0x03: /* l.bnf */
- case 0x04: /* l.bf */
- {
- TCGLabel *lab = gen_new_label();
- TCGv sr_f = tcg_temp_new();
- tcg_gen_movi_tl(jmp_pc, dc->pc+8);
- tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
- tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
- sr_f, SR_F, lab);
- tcg_gen_movi_tl(jmp_pc, tmp_pc);
- gen_set_label(lab);
- tcg_temp_free(sr_f);
- }
- break;
- case 0x11: /* l.jr */
- tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
- break;
- case 0x12: /* l.jalr */
- tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
- tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
- break;
- default:
- gen_illegal_exception(dc);
- break;
+static void gen_ove_ov(DisasContext *dc)
+{
+ if (dc->tb_flags & SR_OVE) {
+ gen_helper_ove_ov(cpu_env);
}
+}
- dc->delayed_branch = 2;
- dc->tb_flags |= D_FLAG;
- gen_sync_flags(dc);
-}
-
-
-static void dec_calc(DisasContext *dc, uint32_t insn)
-{
- uint32_t op0, op1, op2;
- uint32_t ra, rb, rd;
- op0 = extract32(insn, 0, 4);
- op1 = extract32(insn, 8, 2);
- op2 = extract32(insn, 6, 2);
- ra = extract32(insn, 16, 5);
- rb = extract32(insn, 11, 5);
- rd = extract32(insn, 21, 5);
-
- switch (op0) {
- case 0x0000:
- switch (op1) {
- case 0x00: /* l.add */
- LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb);
- {
- TCGLabel *lab = gen_new_label();
- TCGv_i64 ta = tcg_temp_new_i64();
- TCGv_i64 tb = tcg_temp_new_i64();
- TCGv_i64 td = tcg_temp_local_new_i64();
- TCGv_i32 res = tcg_temp_local_new_i32();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
- tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
- tcg_gen_add_i64(td, ta, tb);
- tcg_gen_extrl_i64_i32(res, td);
- tcg_gen_shri_i64(td, td, 31);
- tcg_gen_andi_i64(td, td, 0x3);
- /* Jump to lab when no overflow. */
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
- tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab);
- tcg_gen_mov_i32(cpu_R[rd], res);
- tcg_temp_free_i64(ta);
- tcg_temp_free_i64(tb);
- tcg_temp_free_i64(td);
- tcg_temp_free_i32(res);
- tcg_temp_free_i32(sr_ove);
- }
- break;
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x0001: /* l.addc */
- switch (op1) {
- case 0x00:
- LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb);
- {
- TCGLabel *lab = gen_new_label();
- TCGv_i64 ta = tcg_temp_new_i64();
- TCGv_i64 tb = tcg_temp_new_i64();
- TCGv_i64 tcy = tcg_temp_local_new_i64();
- TCGv_i64 td = tcg_temp_local_new_i64();
- TCGv_i32 res = tcg_temp_local_new_i32();
- TCGv_i32 sr_cy = tcg_temp_local_new_i32();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
- tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
- tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
- tcg_gen_extu_i32_i64(tcy, sr_cy);
- tcg_gen_shri_i64(tcy, tcy, 10);
- tcg_gen_add_i64(td, ta, tb);
- tcg_gen_add_i64(td, td, tcy);
- tcg_gen_extrl_i64_i32(res, td);
- tcg_gen_shri_i64(td, td, 32);
- tcg_gen_andi_i64(td, td, 0x3);
- /* Jump to lab when no overflow. */
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
- tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab);
- tcg_gen_mov_i32(cpu_R[rd], res);
- tcg_temp_free_i64(ta);
- tcg_temp_free_i64(tb);
- tcg_temp_free_i64(tcy);
- tcg_temp_free_i64(td);
- tcg_temp_free_i32(res);
- tcg_temp_free_i32(sr_cy);
- tcg_temp_free_i32(sr_ove);
- }
- break;
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x0002: /* l.sub */
- switch (op1) {
- case 0x00:
- LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb);
- {
- TCGLabel *lab = gen_new_label();
- TCGv_i64 ta = tcg_temp_new_i64();
- TCGv_i64 tb = tcg_temp_new_i64();
- TCGv_i64 td = tcg_temp_local_new_i64();
- TCGv_i32 res = tcg_temp_local_new_i32();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
-
- tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
- tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
- tcg_gen_sub_i64(td, ta, tb);
- tcg_gen_extrl_i64_i32(res, td);
- tcg_gen_shri_i64(td, td, 31);
- tcg_gen_andi_i64(td, td, 0x3);
- /* Jump to lab when no overflow. */
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
- tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab);
- tcg_gen_mov_i32(cpu_R[rd], res);
- tcg_temp_free_i64(ta);
- tcg_temp_free_i64(tb);
- tcg_temp_free_i64(td);
- tcg_temp_free_i32(res);
- tcg_temp_free_i32(sr_ove);
- }
- break;
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
+static void gen_ove_cyov(DisasContext *dc)
+{
+ if (dc->tb_flags & SR_OVE) {
+ gen_helper_ove_cyov(cpu_env);
+ }
+}
- case 0x0003: /* l.and */
- switch (op1) {
- case 0x00:
- LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb);
- tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
- break;
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
+static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
+{
+ TCGv t0 = tcg_const_tl(0);
+ TCGv res = tcg_temp_new();
- case 0x0004: /* l.or */
- switch (op1) {
- case 0x00:
- LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb);
- tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
- break;
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
+ tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, srcb, t0);
+ tcg_gen_xor_tl(cpu_sr_ov, srca, srcb);
+ tcg_gen_xor_tl(t0, res, srcb);
+ tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov);
+ tcg_temp_free(t0);
- case 0x0005:
- switch (op1) {
- case 0x00: /* l.xor */
- LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb);
- tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
- break;
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x0006:
- switch (op1) {
- case 0x03: /* l.mul */
- LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb);
- if (ra != 0 && rb != 0) {
- gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- } else {
- tcg_gen_movi_tl(cpu_R[rd], 0x0);
- }
- break;
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x0009:
- switch (op1) {
- case 0x03: /* l.div */
- LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
- {
- TCGLabel *lab0 = gen_new_label();
- TCGLabel *lab1 = gen_new_label();
- TCGLabel *lab2 = gen_new_label();
- TCGLabel *lab3 = gen_new_label();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- if (rb == 0) {
- tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab0);
- } else {
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[rb],
- 0x00000000, lab1);
- tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[ra],
- 0x80000000, lab2);
- tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
- 0xffffffff, lab2);
- gen_set_label(lab1);
- tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab3);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab2);
- tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
- gen_set_label(lab3);
- }
- tcg_temp_free_i32(sr_ove);
- }
- break;
+ tcg_gen_mov_tl(dest, res);
+ tcg_temp_free(res);
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x000a:
- switch (op1) {
- case 0x03: /* l.divu */
- LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb);
- {
- TCGLabel *lab0 = gen_new_label();
- TCGLabel *lab1 = gen_new_label();
- TCGLabel *lab2 = gen_new_label();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- if (rb == 0) {
- tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab0);
- } else {
- tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
- 0x00000000, lab1);
- tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab2);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab1);
- tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
- gen_set_label(lab2);
- }
- tcg_temp_free_i32(sr_ove);
- }
- break;
+ gen_ove_cyov(dc);
+}
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x000b:
- switch (op1) {
- case 0x03: /* l.mulu */
- LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb);
- if (rb != 0 && ra != 0) {
- TCGv_i64 result = tcg_temp_local_new_i64();
- TCGv_i64 tra = tcg_temp_local_new_i64();
- TCGv_i64 trb = tcg_temp_local_new_i64();
- TCGv_i64 high = tcg_temp_new_i64();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- TCGLabel *lab = gen_new_label();
- /* Calculate each result. */
- tcg_gen_extu_i32_i64(tra, cpu_R[ra]);
- tcg_gen_extu_i32_i64(trb, cpu_R[rb]);
- tcg_gen_mul_i64(result, tra, trb);
- tcg_temp_free_i64(tra);
- tcg_temp_free_i64(trb);
- tcg_gen_shri_i64(high, result, TARGET_LONG_BITS);
- /* Overflow or not. */
- tcg_gen_brcondi_i64(TCG_COND_EQ, high, 0x00000000, lab);
- tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab);
- tcg_temp_free_i64(high);
- tcg_gen_trunc_i64_tl(cpu_R[rd], result);
- tcg_temp_free_i64(result);
- tcg_temp_free_i32(sr_ove);
- } else {
- tcg_gen_movi_tl(cpu_R[rd], 0);
- }
- break;
+static void gen_addc(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
+{
+ TCGv t0 = tcg_const_tl(0);
+ TCGv res = tcg_temp_new();
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x000e:
- switch (op1) {
- case 0x00: /* l.cmov */
- LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
- {
- TCGLabel *lab = gen_new_label();
- TCGv res = tcg_temp_local_new();
- TCGv sr_f = tcg_temp_new();
- tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
- tcg_gen_mov_tl(res, cpu_R[rb]);
- tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
- tcg_gen_mov_tl(res, cpu_R[ra]);
- gen_set_label(lab);
- tcg_gen_mov_tl(cpu_R[rd], res);
- tcg_temp_free(sr_f);
- tcg_temp_free(res);
- }
- break;
+ tcg_gen_add2_tl(res, cpu_sr_cy, srca, t0, cpu_sr_cy, t0);
+ tcg_gen_add2_tl(res, cpu_sr_cy, res, cpu_sr_cy, srcb, t0);
+ tcg_gen_xor_tl(cpu_sr_ov, srca, srcb);
+ tcg_gen_xor_tl(t0, res, srcb);
+ tcg_gen_andc_tl(cpu_sr_ov, t0, cpu_sr_ov);
+ tcg_temp_free(t0);
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x000f:
- switch (op1) {
- case 0x00: /* l.ff1 */
- LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb);
- tcg_gen_ctzi_tl(cpu_R[rd], cpu_R[ra], -1);
- tcg_gen_addi_tl(cpu_R[rd], cpu_R[rd], 1);
- break;
- case 0x01: /* l.fl1 */
- LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb);
- tcg_gen_clzi_tl(cpu_R[rd], cpu_R[ra], TARGET_LONG_BITS);
- tcg_gen_subfi_tl(cpu_R[rd], TARGET_LONG_BITS, cpu_R[rd]);
- break;
+ tcg_gen_mov_tl(dest, res);
+ tcg_temp_free(res);
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x0008:
- switch (op1) {
- case 0x00:
- switch (op2) {
- case 0x00: /* l.sll */
- LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb);
- tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
- break;
- case 0x01: /* l.srl */
- LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb);
- tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
- break;
- case 0x02: /* l.sra */
- LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb);
- tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
- break;
- case 0x03: /* l.ror */
- LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb);
- tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
- break;
-
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
+ gen_ove_cyov(dc);
+}
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x000c:
- switch (op1) {
- case 0x00:
- switch (op2) {
- case 0x00: /* l.exths */
- LOG_DIS("l.exths r%d, r%d\n", rd, ra);
- tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]);
- break;
- case 0x01: /* l.extbs */
- LOG_DIS("l.extbs r%d, r%d\n", rd, ra);
- tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]);
- break;
- case 0x02: /* l.exthz */
- LOG_DIS("l.exthz r%d, r%d\n", rd, ra);
- tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]);
- break;
- case 0x03: /* l.extbz */
- LOG_DIS("l.extbz r%d, r%d\n", rd, ra);
- tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]);
- break;
-
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
+static void gen_sub(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
+{
+ TCGv res = tcg_temp_new();
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x000d:
- switch (op1) {
- case 0x00:
- switch (op2) {
- case 0x00: /* l.extws */
- LOG_DIS("l.extws r%d, r%d\n", rd, ra);
- tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]);
- break;
- case 0x01: /* l.extwz */
- LOG_DIS("l.extwz r%d, r%d\n", rd, ra);
- tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]);
- break;
-
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
+ tcg_gen_sub_tl(res, srca, srcb);
+ tcg_gen_xor_tl(cpu_sr_cy, srca, srcb);
+ tcg_gen_xor_tl(cpu_sr_ov, res, srcb);
+ tcg_gen_and_tl(cpu_sr_ov, cpu_sr_ov, cpu_sr_cy);
+ tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_cy, srca, srcb);
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
+ tcg_gen_mov_tl(dest, res);
+ tcg_temp_free(res);
- default:
- gen_illegal_exception(dc);
- break;
- }
+ gen_ove_cyov(dc);
}
-static void dec_misc(DisasContext *dc, uint32_t insn)
+static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
{
- uint32_t op0, op1;
- uint32_t ra, rb, rd;
-#ifdef OPENRISC_DISAS
- uint32_t L6, K5;
-#endif
- uint32_t I16, I5, I11, N26, tmp;
- TCGMemOp mop;
-
- op0 = extract32(insn, 26, 6);
- op1 = extract32(insn, 24, 2);
- ra = extract32(insn, 16, 5);
- rb = extract32(insn, 11, 5);
- rd = extract32(insn, 21, 5);
-#ifdef OPENRISC_DISAS
- L6 = extract32(insn, 5, 6);
- K5 = extract32(insn, 0, 5);
-#endif
- I16 = extract32(insn, 0, 16);
- I5 = extract32(insn, 21, 5);
- I11 = extract32(insn, 0, 11);
- N26 = extract32(insn, 0, 26);
- tmp = (I5<<11) + I11;
-
- switch (op0) {
- case 0x00: /* l.j */
- LOG_DIS("l.j %d\n", N26);
- gen_jump(dc, N26, 0, op0);
- break;
-
- case 0x01: /* l.jal */
- LOG_DIS("l.jal %d\n", N26);
- gen_jump(dc, N26, 0, op0);
- break;
-
- case 0x03: /* l.bnf */
- LOG_DIS("l.bnf %d\n", N26);
- gen_jump(dc, N26, 0, op0);
- break;
-
- case 0x04: /* l.bf */
- LOG_DIS("l.bf %d\n", N26);
- gen_jump(dc, N26, 0, op0);
- break;
-
- case 0x05:
- switch (op1) {
- case 0x01: /* l.nop */
- LOG_DIS("l.nop %d\n", I16);
- break;
+ TCGv t0 = tcg_temp_new();
- default:
- gen_illegal_exception(dc);
- break;
- }
- break;
-
- case 0x11: /* l.jr */
- LOG_DIS("l.jr r%d\n", rb);
- gen_jump(dc, 0, rb, op0);
- break;
-
- case 0x12: /* l.jalr */
- LOG_DIS("l.jalr r%d\n", rb);
- gen_jump(dc, 0, rb, op0);
- break;
-
- case 0x13: /* l.maci */
- LOG_DIS("l.maci %d, r%d, %d\n", I5, ra, I11);
- {
- TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 t2 = tcg_temp_new_i64();
- TCGv_i32 dst = tcg_temp_new_i32();
- TCGv ttmp = tcg_const_tl(tmp);
- tcg_gen_mul_tl(dst, cpu_R[ra], ttmp);
- tcg_gen_ext_i32_i64(t1, dst);
- tcg_gen_concat_i32_i64(t2, maclo, machi);
- tcg_gen_add_i64(t2, t2, t1);
- tcg_gen_extrl_i64_i32(maclo, t2);
- tcg_gen_shri_i64(t2, t2, 32);
- tcg_gen_extrl_i64_i32(machi, t2);
- tcg_temp_free_i32(dst);
- tcg_temp_free(ttmp);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
- }
- break;
-
- case 0x09: /* l.rfe */
- LOG_DIS("l.rfe\n");
- {
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
- gen_helper_rfe(cpu_env);
- dc->is_jmp = DISAS_UPDATE;
-#endif
- }
- break;
+ tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb);
+ tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1);
+ tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0);
+ tcg_temp_free(t0);
- case 0x1c: /* l.cust1 */
- LOG_DIS("l.cust1\n");
- break;
+ tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);
+ gen_ove_ov(dc);
+}
- case 0x1d: /* l.cust2 */
- LOG_DIS("l.cust2\n");
- break;
+static void gen_mulu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
+{
+ tcg_gen_muls2_tl(dest, cpu_sr_cy, srca, srcb);
+ tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_cy, cpu_sr_cy, 0);
- case 0x1e: /* l.cust3 */
- LOG_DIS("l.cust3\n");
- break;
+ gen_ove_cy(dc);
+}
- case 0x1f: /* l.cust4 */
- LOG_DIS("l.cust4\n");
- break;
+static void gen_div(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
+{
+ TCGv t0 = tcg_temp_new();
- case 0x3c: /* l.cust5 */
- LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5);
- break;
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_ov, srcb, 0);
+ /* The result of divide-by-zero is undefined.
+ Supress the host-side exception by dividing by 1. */
+ tcg_gen_or_tl(t0, srcb, cpu_sr_ov);
+ tcg_gen_div_tl(dest, srca, t0);
+ tcg_temp_free(t0);
- case 0x3d: /* l.cust6 */
- LOG_DIS("l.cust6\n");
- break;
+ tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);
+ gen_ove_ov(dc);
+}
- case 0x3e: /* l.cust7 */
- LOG_DIS("l.cust7\n");
- break;
+static void gen_divu(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb)
+{
+ TCGv t0 = tcg_temp_new();
- case 0x3f: /* l.cust8 */
- LOG_DIS("l.cust8\n");
- break;
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_cy, srcb, 0);
+ /* The result of divide-by-zero is undefined.
+ Supress the host-side exception by dividing by 1. */
+ tcg_gen_or_tl(t0, srcb, cpu_sr_cy);
+ tcg_gen_divu_tl(dest, srca, t0);
+ tcg_temp_free(t0);
-/* not used yet, open it when we need or64. */
-/*#ifdef TARGET_OPENRISC64
- case 0x20: l.ld
- LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
- check_ob64s(dc);
- mop = MO_TEQ;
- goto do_load;
-#endif*/
+ gen_ove_cy(dc);
+}
- case 0x21: /* l.lwz */
- LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16);
- mop = MO_TEUL;
- goto do_load;
-
- case 0x22: /* l.lws */
- LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16);
- mop = MO_TESL;
- goto do_load;
-
- case 0x23: /* l.lbz */
- LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16);
- mop = MO_UB;
- goto do_load;
-
- case 0x24: /* l.lbs */
- LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16);
- mop = MO_SB;
- goto do_load;
-
- case 0x25: /* l.lhz */
- LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16);
- mop = MO_TEUW;
- goto do_load;
-
- case 0x26: /* l.lhs */
- LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16);
- mop = MO_TESW;
- goto do_load;
-
- do_load:
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
- tcg_gen_qemu_ld_tl(cpu_R[rd], t0, dc->mem_idx, mop);
- tcg_temp_free(t0);
- }
- break;
-
- case 0x27: /* l.addi */
- LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
- {
- if (I16 == 0) {
- tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
- } else {
- TCGLabel *lab = gen_new_label();
- TCGv_i64 ta = tcg_temp_new_i64();
- TCGv_i64 td = tcg_temp_local_new_i64();
- TCGv_i32 res = tcg_temp_local_new_i32();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
- tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
- tcg_gen_extrl_i64_i32(res, td);
- tcg_gen_shri_i64(td, td, 32);
- tcg_gen_andi_i64(td, td, 0x3);
- /* Jump to lab when no overflow. */
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
- tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab);
- tcg_gen_mov_i32(cpu_R[rd], res);
- tcg_temp_free_i64(ta);
- tcg_temp_free_i64(td);
- tcg_temp_free_i32(res);
- tcg_temp_free_i32(sr_ove);
- }
- }
- break;
-
- case 0x28: /* l.addic */
- LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16);
- {
- TCGLabel *lab = gen_new_label();
- TCGv_i64 ta = tcg_temp_new_i64();
- TCGv_i64 td = tcg_temp_local_new_i64();
- TCGv_i64 tcy = tcg_temp_local_new_i64();
- TCGv_i32 res = tcg_temp_local_new_i32();
- TCGv_i32 sr_cy = tcg_temp_local_new_i32();
- TCGv_i32 sr_ove = tcg_temp_local_new_i32();
- tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
- tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
- tcg_gen_shri_i32(sr_cy, sr_cy, 10);
- tcg_gen_extu_i32_i64(tcy, sr_cy);
- tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
- tcg_gen_add_i64(td, td, tcy);
- tcg_gen_extrl_i64_i32(res, td);
- tcg_gen_shri_i64(td, td, 32);
- tcg_gen_andi_i64(td, td, 0x3);
- /* Jump to lab when no overflow. */
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
- tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
- tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
- tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
- tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
- gen_exception(dc, EXCP_RANGE);
- gen_set_label(lab);
- tcg_gen_mov_i32(cpu_R[rd], res);
- tcg_temp_free_i64(ta);
- tcg_temp_free_i64(td);
- tcg_temp_free_i64(tcy);
- tcg_temp_free_i32(res);
- tcg_temp_free_i32(sr_cy);
- tcg_temp_free_i32(sr_ove);
- }
- break;
-
- case 0x29: /* l.andi */
- LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, I16);
- tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
- break;
-
- case 0x2a: /* l.ori */
- LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, I16);
- tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
- break;
-
- case 0x2b: /* l.xori */
- LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16);
- tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], sign_extend(I16, 16));
- break;
-
- case 0x2c: /* l.muli */
- LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16);
- if (ra != 0 && I16 != 0) {
- TCGv_i32 im = tcg_const_i32(I16);
- gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], im);
- tcg_temp_free_i32(im);
- } else {
- tcg_gen_movi_tl(cpu_R[rd], 0x0);
- }
- break;
+static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_ext_tl_i64(t1, srca);
+ tcg_gen_ext_tl_i64(t2, srcb);
+ if (TARGET_LONG_BITS == 32) {
+ tcg_gen_mul_i64(cpu_mac, t1, t2);
+ tcg_gen_movi_tl(cpu_sr_ov, 0);
+ } else {
+ TCGv_i64 high = tcg_temp_new_i64();
- case 0x2d: /* l.mfspr */
- LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16);
- {
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- TCGv_i32 ti = tcg_const_i32(I16);
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
- gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti);
- tcg_temp_free_i32(ti);
-#endif
- }
- break;
+ tcg_gen_muls2_i64(cpu_mac, high, t1, t2);
+ tcg_gen_sari_i64(t1, cpu_mac, 63);
+ tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high);
+ tcg_temp_free_i64(high);
+ tcg_gen_trunc_i64_tl(cpu_sr_ov, t1);
+ tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);
- case 0x30: /* l.mtspr */
- LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- {
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- TCGv_i32 im = tcg_const_i32(tmp);
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
- gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im);
- tcg_temp_free_i32(im);
-#endif
- }
- break;
+ gen_ove_ov(dc);
+ }
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
-/* not used yet, open it when we need or64. */
-/*#ifdef TARGET_OPENRISC64
- case 0x34: l.sd
- LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- check_ob64s(dc);
- mop = MO_TEQ;
- goto do_store;
-#endif*/
+static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extu_tl_i64(t1, srca);
+ tcg_gen_extu_tl_i64(t2, srcb);
+ if (TARGET_LONG_BITS == 32) {
+ tcg_gen_mul_i64(cpu_mac, t1, t2);
+ tcg_gen_movi_tl(cpu_sr_cy, 0);
+ } else {
+ TCGv_i64 high = tcg_temp_new_i64();
- case 0x35: /* l.sw */
- LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- mop = MO_TEUL;
- goto do_store;
-
- case 0x36: /* l.sb */
- LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- mop = MO_UB;
- goto do_store;
-
- case 0x37: /* l.sh */
- LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11);
- mop = MO_TEUW;
- goto do_store;
-
- do_store:
- {
- TCGv t0 = tcg_temp_new();
- tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
- tcg_gen_qemu_st_tl(cpu_R[rb], t0, dc->mem_idx, mop);
- tcg_temp_free(t0);
- }
- break;
+ tcg_gen_mulu2_i64(cpu_mac, high, t1, t2);
+ tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0);
+ tcg_gen_trunc_i64_tl(cpu_sr_cy, high);
+ tcg_temp_free_i64(high);
- default:
- gen_illegal_exception(dc);
- break;
+ gen_ove_cy(dc);
}
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
}
-static void dec_mac(DisasContext *dc, uint32_t insn)
-{
- uint32_t op0;
- uint32_t ra, rb;
- op0 = extract32(insn, 0, 4);
- ra = extract32(insn, 16, 5);
- rb = extract32(insn, 11, 5);
-
- switch (op0) {
- case 0x0001: /* l.mac */
- LOG_DIS("l.mac r%d, r%d\n", ra, rb);
- {
- TCGv_i32 t0 = tcg_temp_new_i32();
- TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 t2 = tcg_temp_new_i64();
- tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
- tcg_gen_ext_i32_i64(t1, t0);
- tcg_gen_concat_i32_i64(t2, maclo, machi);
- tcg_gen_add_i64(t2, t2, t1);
- tcg_gen_extrl_i64_i32(maclo, t2);
- tcg_gen_shri_i64(t2, t2, 32);
- tcg_gen_extrl_i64_i32(machi, t2);
- tcg_temp_free_i32(t0);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
- }
- break;
-
- case 0x0002: /* l.msb */
- LOG_DIS("l.msb r%d, r%d\n", ra, rb);
- {
- TCGv_i32 t0 = tcg_temp_new_i32();
- TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 t2 = tcg_temp_new_i64();
- tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
- tcg_gen_ext_i32_i64(t1, t0);
- tcg_gen_concat_i32_i64(t2, maclo, machi);
- tcg_gen_sub_i64(t2, t2, t1);
- tcg_gen_extrl_i64_i32(maclo, t2);
- tcg_gen_shri_i64(t2, t2, 32);
- tcg_gen_extrl_i64_i32(machi, t2);
- tcg_temp_free_i32(t0);
- tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
- }
- break;
+static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_ext_tl_i64(t1, srca);
+ tcg_gen_ext_tl_i64(t2, srcb);
+ tcg_gen_mul_i64(t1, t1, t2);
+
+ /* Note that overflow is only computed during addition stage. */
+ tcg_gen_xor_i64(t2, cpu_mac, t1);
+ tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
+ tcg_gen_xor_i64(t1, t1, cpu_mac);
+ tcg_gen_andc_i64(t1, t1, t2);
+ tcg_temp_free_i64(t2);
+
+#if TARGET_LONG_BITS == 32
+ tcg_gen_extrh_i64_i32(cpu_sr_ov, t1);
+#else
+ tcg_gen_mov_i64(cpu_sr_ov, t1);
+#endif
+ tcg_temp_free_i64(t1);
- default:
- gen_illegal_exception(dc);
- break;
- }
+ gen_ove_ov(dc);
}
-static void dec_logic(DisasContext *dc, uint32_t insn)
+static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb)
{
- uint32_t op0;
- uint32_t rd, ra, L6;
- op0 = extract32(insn, 6, 2);
- rd = extract32(insn, 21, 5);
- ra = extract32(insn, 16, 5);
- L6 = extract32(insn, 0, 6);
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
- switch (op0) {
- case 0x00: /* l.slli */
- LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6);
- tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
- break;
+ tcg_gen_extu_tl_i64(t1, srca);
+ tcg_gen_extu_tl_i64(t2, srcb);
+ tcg_gen_mul_i64(t1, t1, t2);
+ tcg_temp_free_i64(t2);
- case 0x01: /* l.srli */
- LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6);
- tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
- break;
+ /* Note that overflow is only computed during addition stage. */
+ tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
+ tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1);
+ tcg_gen_trunc_i64_tl(cpu_sr_cy, t1);
+ tcg_temp_free_i64(t1);
- case 0x02: /* l.srai */
- LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6);
- tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); break;
+ gen_ove_cy(dc);
+}
- case 0x03: /* l.rori */
- LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6);
- tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
- break;
+static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_ext_tl_i64(t1, srca);
+ tcg_gen_ext_tl_i64(t2, srcb);
+ tcg_gen_mul_i64(t1, t1, t2);
+
+ /* Note that overflow is only computed during subtraction stage. */
+ tcg_gen_xor_i64(t2, cpu_mac, t1);
+ tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
+ tcg_gen_xor_i64(t1, t1, cpu_mac);
+ tcg_gen_and_i64(t1, t1, t2);
+ tcg_temp_free_i64(t2);
+
+#if TARGET_LONG_BITS == 32
+ tcg_gen_extrh_i64_i32(cpu_sr_ov, t1);
+#else
+ tcg_gen_mov_i64(cpu_sr_ov, t1);
+#endif
+ tcg_temp_free_i64(t1);
- default:
- gen_illegal_exception(dc);
- break;
- }
+ gen_ove_ov(dc);
}
-static void dec_M(DisasContext *dc, uint32_t insn)
+static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb)
{
- uint32_t op0;
- uint32_t rd;
- uint32_t K16;
- op0 = extract32(insn, 16, 1);
- rd = extract32(insn, 21, 5);
- K16 = extract32(insn, 0, 16);
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
- switch (op0) {
- case 0x0: /* l.movhi */
- LOG_DIS("l.movhi r%d, %d\n", rd, K16);
- tcg_gen_movi_tl(cpu_R[rd], (K16 << 16));
- break;
+ tcg_gen_extu_tl_i64(t1, srca);
+ tcg_gen_extu_tl_i64(t2, srcb);
+ tcg_gen_mul_i64(t1, t1, t2);
- case 0x1: /* l.macrc */
- LOG_DIS("l.macrc r%d\n", rd);
- tcg_gen_mov_tl(cpu_R[rd], maclo);
- tcg_gen_movi_tl(maclo, 0x0);
- tcg_gen_movi_tl(machi, 0x0);
- break;
+ /* Note that overflow is only computed during subtraction stage. */
+ tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1);
+ tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
+ tcg_gen_trunc_i64_tl(cpu_sr_cy, t2);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t1);
- default:
- gen_illegal_exception(dc);
- break;
- }
+ gen_ove_cy(dc);
}
-static void dec_comp(DisasContext *dc, uint32_t insn)
-{
- uint32_t op0;
- uint32_t ra, rb;
-
- op0 = extract32(insn, 21, 5);
- ra = extract32(insn, 16, 5);
- rb = extract32(insn, 11, 5);
-
- tcg_gen_movi_i32(env_btaken, 0x0);
- /* unsigned integers */
- tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]);
- tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]);
-
- switch (op0) {
- case 0x0: /* l.sfeq */
- LOG_DIS("l.sfeq r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x1: /* l.sfne */
- LOG_DIS("l.sfne r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_NE, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x2: /* l.sfgtu */
- LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x3: /* l.sfgeu */
- LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x4: /* l.sfltu */
- LOG_DIS("l.sfltu r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x5: /* l.sfleu */
- LOG_DIS("l.sfleu r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0xa: /* l.sfgts */
- LOG_DIS("l.sfgts r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_GT, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0xb: /* l.sfges */
- LOG_DIS("l.sfges r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_GE, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0xc: /* l.sflts */
- LOG_DIS("l.sflts r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_LT, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0xd: /* l.sfles */
- LOG_DIS("l.sfles r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_LE, env_btaken, cpu_R[ra], cpu_R[rb]);
- break;
-
- default:
- gen_illegal_exception(dc);
- break;
- }
- wb_SR_F();
+static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.add r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
}
-static void dec_compi(DisasContext *dc, uint32_t insn)
+static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- uint32_t op0;
- uint32_t ra, I16;
+ LOG_DIS("l.addc r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- op0 = extract32(insn, 21, 5);
- ra = extract32(insn, 16, 5);
- I16 = extract32(insn, 0, 16);
+static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.sub r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- tcg_gen_movi_i32(env_btaken, 0x0);
- I16 = sign_extend(I16, 16);
+static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.and r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- switch (op0) {
- case 0x0: /* l.sfeqi */
- LOG_DIS("l.sfeqi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.or r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0x1: /* l.sfnei */
- LOG_DIS("l.sfnei r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_NE, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.xor r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0x2: /* l.sfgtui */
- LOG_DIS("l.sfgtui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.sll r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0x3: /* l.sfgeui */
- LOG_DIS("l.sfgeui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.srl r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0x4: /* l.sfltui */
- LOG_DIS("l.sfltui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.sra r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0x5: /* l.sfleui */
- LOG_DIS("l.sfleui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.ror r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0xa: /* l.sfgtsi */
- LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GT, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn)
+{
+ LOG_DIS("l.exths r%d, r%d\n", a->d, a->a);
+ check_r0_write(a->d);
+ tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]);
+ return true;
+}
- case 0xb: /* l.sfgesi */
- LOG_DIS("l.sfgesi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GE, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn)
+{
+ LOG_DIS("l.extbs r%d, r%d\n", a->d, a->a);
+ check_r0_write(a->d);
+ tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]);
+ return true;
+}
- case 0xc: /* l.sfltsi */
- LOG_DIS("l.sfltsi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LT, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn)
+{
+ LOG_DIS("l.exthz r%d, r%d\n", a->d, a->a);
+ check_r0_write(a->d);
+ tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]);
+ return true;
+}
- case 0xd: /* l.sflesi */
- LOG_DIS("l.sflesi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LE, env_btaken, cpu_R[ra], I16);
- break;
+static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn)
+{
+ LOG_DIS("l.extbz r%d, r%d\n", a->d, a->a);
+ check_r0_write(a->d);
+ tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]);
+ return true;
+}
- default:
- gen_illegal_exception(dc);
- break;
- }
- wb_SR_F();
+static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ TCGv zero;
+ LOG_DIS("l.cmov r%d, r%d, r%d\n", a->d, a->a, a->b);
+
+ check_r0_write(a->d);
+ zero = tcg_const_tl(0);
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[a->d], cpu_sr_f, zero,
+ cpu_R[a->a], cpu_R[a->b]);
+ tcg_temp_free(zero);
+ return true;
}
-static void dec_sys(DisasContext *dc, uint32_t insn)
+static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn)
{
- uint32_t op0;
-#ifdef OPENRISC_DISAS
- uint32_t K16;
-#endif
- op0 = extract32(insn, 16, 10);
-#ifdef OPENRISC_DISAS
- K16 = extract32(insn, 0, 16);
-#endif
+ LOG_DIS("l.ff1 r%d, r%d\n", a->d, a->a);
- switch (op0) {
- case 0x000: /* l.sys */
- LOG_DIS("l.sys %d\n", K16);
- tcg_gen_movi_tl(cpu_pc, dc->pc);
- gen_exception(dc, EXCP_SYSCALL);
- dc->is_jmp = DISAS_UPDATE;
- break;
-
- case 0x100: /* l.trap */
- LOG_DIS("l.trap %d\n", K16);
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
- tcg_gen_movi_tl(cpu_pc, dc->pc);
- gen_exception(dc, EXCP_TRAP);
-#endif
- break;
+ check_r0_write(a->d);
+ tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1);
+ tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1);
+ return true;
+}
- case 0x300: /* l.csync */
- LOG_DIS("l.csync\n");
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
-#endif
- break;
+static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn)
+{
+ LOG_DIS("l.fl1 r%d, r%d\n", a->d, a->a);
- case 0x200: /* l.msync */
- LOG_DIS("l.msync\n");
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
-#endif
- break;
+ check_r0_write(a->d);
+ tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS);
+ tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]);
+ return true;
+}
- case 0x270: /* l.psync */
- LOG_DIS("l.psync\n");
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
-#endif
- break;
+static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.mul r%d, r%d, r%d\n", a->d, a->a, a->b);
- default:
- gen_illegal_exception(dc);
- break;
- }
+ check_r0_write(a->d);
+ gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
}
-static void dec_float(DisasContext *dc, uint32_t insn)
+static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- uint32_t op0;
- uint32_t ra, rb, rd;
- op0 = extract32(insn, 0, 8);
- ra = extract32(insn, 16, 5);
- rb = extract32(insn, 11, 5);
- rd = extract32(insn, 21, 5);
+ LOG_DIS("l.mulu r%d, r%d, r%d\n", a->d, a->a, a->b);
- switch (op0) {
- case 0x00: /* lf.add.s */
- LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb);
- gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
+ check_r0_write(a->d);
+ gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0x01: /* lf.sub.s */
- LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb);
- gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
+static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.div r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- case 0x02: /* lf.mul.s */
- LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb);
- if (ra != 0 && rb != 0) {
- gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- } else {
- tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
- tcg_gen_movi_i32(cpu_R[rd], 0x0);
- }
- break;
-
- case 0x03: /* lf.div.s */
- LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb);
- gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x04: /* lf.itof.s */
- LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
- gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]);
- break;
-
- case 0x05: /* lf.ftoi.s */
- LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
- gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]);
- break;
-
- case 0x06: /* lf.rem.s */
- LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb);
- gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x07: /* lf.madd.s */
- LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb);
- gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x08: /* lf.sfeq.s */
- LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb);
- gen_helper_float_eq_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x09: /* lf.sfne.s */
- LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb);
- gen_helper_float_ne_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x0a: /* lf.sfgt.s */
- LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb);
- gen_helper_float_gt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x0b: /* lf.sfge.s */
- LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb);
- gen_helper_float_ge_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x0c: /* lf.sflt.s */
- LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb);
- gen_helper_float_lt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x0d: /* lf.sfle.s */
- LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb);
- gen_helper_float_le_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
+static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("l.divu r%d, r%d, r%d\n", a->d, a->a, a->b);
-/* not used yet, open it when we need or64. */
-/*#ifdef TARGET_OPENRISC64
- case 0x10: lf.add.d
- LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb);
- check_of64s(dc);
- gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x11: lf.sub.d
- LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb);
- check_of64s(dc);
- gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x12: lf.mul.d
- LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb);
- check_of64s(dc);
- if (ra != 0 && rb != 0) {
- gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- } else {
- tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
- tcg_gen_movi_i64(cpu_R[rd], 0x0);
- }
- break;
-
- case 0x13: lf.div.d
- LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb);
- check_of64s(dc);
- gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x14: lf.itof.d
- LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
- check_of64s(dc);
- gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]);
- break;
-
- case 0x15: lf.ftoi.d
- LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
- check_of64s(dc);
- gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]);
- break;
-
- case 0x16: lf.rem.d
- LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb);
- check_of64s(dc);
- gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x17: lf.madd.d
- LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb);
- check_of64s(dc);
- gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x18: lf.sfeq.d
- LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
- check_of64s(dc);
- gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x1a: lf.sfgt.d
- LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
- check_of64s(dc);
- gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x1b: lf.sfge.d
- LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
- check_of64s(dc);
- gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x19: lf.sfne.d
- LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
- check_of64s(dc);
- gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x1c: lf.sflt.d
- LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
- check_of64s(dc);
- gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-
- case 0x1d: lf.sfle.d
- LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
- check_of64s(dc);
- gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
- break;
-#endif*/
+ check_r0_write(a->d);
+ gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- default:
- gen_illegal_exception(dc);
- break;
- }
- wb_SR_F();
+static bool trans_l_muld(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("l.muld r%d, r%d\n", a->a, a->b);
+ gen_muld(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
}
-static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
+static bool trans_l_muldu(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- uint32_t op0;
- uint32_t insn;
- insn = cpu_ldl_code(&cpu->env, dc->pc);
- op0 = extract32(insn, 26, 6);
+ LOG_DIS("l.muldu r%d, r%d\n", a->a, a->b);
+ gen_muldu(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- switch (op0) {
- case 0x06:
- dec_M(dc, insn);
- break;
+static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn)
+{
+ target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
- case 0x08:
- dec_sys(dc, insn);
- break;
+ LOG_DIS("l.j %d\n", a->n);
+ tcg_gen_movi_tl(jmp_pc, tmp_pc);
+ dc->delayed_branch = 2;
+ return true;
+}
- case 0x2e:
- dec_logic(dc, insn);
- break;
+static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn)
+{
+ target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
+ target_ulong ret_pc = dc->base.pc_next + 8;
+
+ LOG_DIS("l.jal %d\n", a->n);
+ tcg_gen_movi_tl(cpu_R[9], ret_pc);
+ /* Optimize jal being used to load the PC for PIC. */
+ if (tmp_pc != ret_pc) {
+ tcg_gen_movi_tl(jmp_pc, tmp_pc);
+ dc->delayed_branch = 2;
+ }
+ return true;
+}
+
+static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond)
+{
+ target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
+ TCGv t_next = tcg_const_tl(dc->base.pc_next + 8);
+ TCGv t_true = tcg_const_tl(tmp_pc);
+ TCGv t_zero = tcg_const_tl(0);
+
+ tcg_gen_movcond_tl(cond, jmp_pc, cpu_sr_f, t_zero, t_true, t_next);
+
+ tcg_temp_free(t_next);
+ tcg_temp_free(t_true);
+ tcg_temp_free(t_zero);
+ dc->delayed_branch = 2;
+}
+
+static bool trans_l_bf(DisasContext *dc, arg_l_bf *a, uint32_t insn)
+{
+ LOG_DIS("l.bf %d\n", a->n);
+ do_bf(dc, a, TCG_COND_NE);
+ return true;
+}
+
+static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a, uint32_t insn)
+{
+ LOG_DIS("l.bnf %d\n", a->n);
+ do_bf(dc, a, TCG_COND_EQ);
+ return true;
+}
+
+static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn)
+{
+ LOG_DIS("l.jr r%d\n", a->b);
+ tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]);
+ dc->delayed_branch = 2;
+ return true;
+}
+
+static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn)
+{
+ LOG_DIS("l.jalr r%d\n", a->b);
+ tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]);
+ tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8);
+ dc->delayed_branch = 2;
+ return true;
+}
+
+static bool trans_l_lwa(DisasContext *dc, arg_load *a, uint32_t insn)
+{
+ TCGv ea;
+
+ LOG_DIS("l.lwa r%d, r%d, %d\n", a->d, a->a, a->i);
+
+ check_r0_write(a->d);
+ ea = tcg_temp_new();
+ tcg_gen_addi_tl(ea, cpu_R[a->a], a->i);
+ tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, MO_TEUL);
+ tcg_gen_mov_tl(cpu_lock_addr, ea);
+ tcg_gen_mov_tl(cpu_lock_value, cpu_R[a->d]);
+ tcg_temp_free(ea);
+ return true;
+}
+
+static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop)
+{
+ TCGv ea;
+
+ check_r0_write(a->d);
+ ea = tcg_temp_new();
+ tcg_gen_addi_tl(ea, cpu_R[a->a], a->i);
+ tcg_gen_qemu_ld_tl(cpu_R[a->d], ea, dc->mem_idx, mop);
+ tcg_temp_free(ea);
+}
+
+static bool trans_l_lwz(DisasContext *dc, arg_load *a, uint32_t insn)
+{
+ LOG_DIS("l.lwz r%d, r%d, %d\n", a->d, a->a, a->i);
+ do_load(dc, a, MO_TEUL);
+ return true;
+}
+
+static bool trans_l_lws(DisasContext *dc, arg_load *a, uint32_t insn)
+{
+ LOG_DIS("l.lws r%d, r%d, %d\n", a->d, a->a, a->i);
+ do_load(dc, a, MO_TESL);
+ return true;
+}
+
+static bool trans_l_lbz(DisasContext *dc, arg_load *a, uint32_t insn)
+{
+ LOG_DIS("l.lbz r%d, r%d, %d\n", a->d, a->a, a->i);
+ do_load(dc, a, MO_UB);
+ return true;
+}
+
+static bool trans_l_lbs(DisasContext *dc, arg_load *a, uint32_t insn)
+{
+ LOG_DIS("l.lbs r%d, r%d, %d\n", a->d, a->a, a->i);
+ do_load(dc, a, MO_SB);
+ return true;
+}
+
+static bool trans_l_lhz(DisasContext *dc, arg_load *a, uint32_t insn)
+{
+ LOG_DIS("l.lhz r%d, r%d, %d\n", a->d, a->a, a->i);
+ do_load(dc, a, MO_TEUW);
+ return true;
+}
+
+static bool trans_l_lhs(DisasContext *dc, arg_load *a, uint32_t insn)
+{
+ LOG_DIS("l.lhs r%d, r%d, %d\n", a->d, a->a, a->i);
+ do_load(dc, a, MO_TESW);
+ return true;
+}
+
+static bool trans_l_swa(DisasContext *dc, arg_store *a, uint32_t insn)
+{
+ TCGv ea, val;
+ TCGLabel *lab_fail, *lab_done;
+
+ LOG_DIS("l.swa r%d, r%d, %d\n", a->a, a->b, a->i);
+
+ ea = tcg_temp_new();
+ tcg_gen_addi_tl(ea, cpu_R[a->a], a->i);
+
+ /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assigned
+ to cpu_R[0]. Since l.swa is quite often immediately followed by a
+ branch, don't bother reallocating; finish the TB using the "real" R0.
+ This also takes care of RB input across the branch. */
+ cpu_R[0] = cpu_R0;
+
+ lab_fail = gen_new_label();
+ lab_done = gen_new_label();
+ tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail);
+ tcg_temp_free(ea);
+
+ val = tcg_temp_new();
+ tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value,
+ cpu_R[a->b], dc->mem_idx, MO_TEUL);
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value);
+ tcg_temp_free(val);
+
+ tcg_gen_br(lab_done);
+
+ gen_set_label(lab_fail);
+ tcg_gen_movi_tl(cpu_sr_f, 0);
+
+ gen_set_label(lab_done);
+ tcg_gen_movi_tl(cpu_lock_addr, -1);
+ return true;
+}
+
+static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_addi_tl(t0, cpu_R[a->a], a->i);
+ tcg_gen_qemu_st_tl(cpu_R[a->b], t0, dc->mem_idx, mop);
+ tcg_temp_free(t0);
+}
+
+static bool trans_l_sw(DisasContext *dc, arg_store *a, uint32_t insn)
+{
+ LOG_DIS("l.sw r%d, r%d, %d\n", a->a, a->b, a->i);
+ do_store(dc, a, MO_TEUL);
+ return true;
+}
+
+static bool trans_l_sb(DisasContext *dc, arg_store *a, uint32_t insn)
+{
+ LOG_DIS("l.sb r%d, r%d, %d\n", a->a, a->b, a->i);
+ do_store(dc, a, MO_UB);
+ return true;
+}
+
+static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn)
+{
+ LOG_DIS("l.sh r%d, r%d, %d\n", a->a, a->b, a->i);
+ do_store(dc, a, MO_TEUW);
+ return true;
+}
+
+static bool trans_l_nop(DisasContext *dc, arg_l_nop *a, uint32_t insn)
+{
+ LOG_DIS("l.nop %d\n", a->k);
+ return true;
+}
+
+static bool trans_l_addi(DisasContext *dc, arg_rri *a, uint32_t insn)
+{
+ TCGv t0;
+
+ LOG_DIS("l.addi r%d, r%d, %d\n", a->d, a->a, a->i);
+ check_r0_write(a->d);
+ t0 = tcg_const_tl(a->i);
+ gen_add(dc, cpu_R[a->d], cpu_R[a->a], t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_l_addic(DisasContext *dc, arg_rri *a, uint32_t insn)
+{
+ TCGv t0;
- case 0x2f:
- dec_compi(dc, insn);
- break;
+ LOG_DIS("l.addic r%d, r%d, %d\n", a->d, a->a, a->i);
+ check_r0_write(a->d);
+ t0 = tcg_const_tl(a->i);
+ gen_addc(dc, cpu_R[a->d], cpu_R[a->a], t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_l_muli(DisasContext *dc, arg_rri *a, uint32_t insn)
+{
+ TCGv t0;
- case 0x31:
- dec_mac(dc, insn);
- break;
+ LOG_DIS("l.muli r%d, r%d, %d\n", a->d, a->a, a->i);
+ check_r0_write(a->d);
+ t0 = tcg_const_tl(a->i);
+ gen_mul(dc, cpu_R[a->d], cpu_R[a->a], t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn)
+{
+ TCGv t0;
+
+ LOG_DIS("l.maci r%d, %d\n", a->a, a->i);
+ t0 = tcg_const_tl(a->i);
+ gen_mac(dc, cpu_R[a->a], t0);
+ tcg_temp_free(t0);
+ return true;
+}
+
+static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn)
+{
+ LOG_DIS("l.andi r%d, r%d, %d\n", a->d, a->a, a->k);
+ check_r0_write(a->d);
+ tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k);
+ return true;
+}
+
+static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn)
+{
+ LOG_DIS("l.ori r%d, r%d, %d\n", a->d, a->a, a->k);
+ check_r0_write(a->d);
+ tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k);
+ return true;
+}
+
+static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn)
+{
+ LOG_DIS("l.xori r%d, r%d, %d\n", a->d, a->a, a->i);
+ check_r0_write(a->d);
+ tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i);
+ return true;
+}
- case 0x32:
- dec_float(dc, insn);
- break;
+static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn)
+{
+ LOG_DIS("l.mfspr r%d, r%d, %d\n", a->d, a->a, a->k);
+ check_r0_write(a->d);
- case 0x38:
- dec_calc(dc, insn);
- break;
+#ifdef CONFIG_USER_ONLY
+ gen_illegal_exception(dc);
+#else
+ if (dc->mem_idx == MMU_USER_IDX) {
+ gen_illegal_exception(dc);
+ } else {
+ TCGv_i32 ti = tcg_const_i32(a->k);
+ gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti);
+ tcg_temp_free_i32(ti);
+ }
+#endif
+ return true;
+}
- case 0x39:
- dec_comp(dc, insn);
- break;
+static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
+{
+ LOG_DIS("l.mtspr r%d, r%d, %d\n", a->a, a->b, a->k);
- default:
- dec_misc(dc, insn);
- break;
+#ifdef CONFIG_USER_ONLY
+ gen_illegal_exception(dc);
+#else
+ if (dc->mem_idx == MMU_USER_IDX) {
+ gen_illegal_exception(dc);
+ } else {
+ TCGv_i32 ti = tcg_const_i32(a->k);
+ gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
+ tcg_temp_free_i32(ti);
}
+#endif
+ return true;
}
-void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
+static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
- struct DisasContext ctx, *dc = &ctx;
- uint32_t pc_start;
- uint32_t next_page_start;
- int num_insns;
- int max_insns;
+ LOG_DIS("l.mac r%d, r%d\n", a->a, a->b);
+ gen_mac(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- pc_start = tb->pc;
- dc->tb = tb;
+static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("l.msb r%d, r%d\n", a->a, a->b);
+ gen_msb(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- dc->is_jmp = DISAS_NEXT;
- dc->ppc = pc_start;
- dc->pc = pc_start;
- dc->flags = cpu->env.cpucfgr;
- dc->mem_idx = cpu_mmu_index(&cpu->env, false);
- dc->synced_flags = dc->tb_flags = tb->flags;
- dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
- dc->singlestep_enabled = cs->singlestep_enabled;
+static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("l.mac r%d, r%d\n", a->a, a->b);
+ gen_macu(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
- num_insns = 0;
- max_insns = tb->cflags & CF_COUNT_MASK;
+static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("l.msb r%d, r%d\n", a->a, a->b);
+ gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn)
+{
+ LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l);
+ check_r0_write(a->d);
+ tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
+ return true;
+}
+
+static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn)
+{
+ LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l);
+ check_r0_write(a->d);
+ tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
+ return true;
+}
+
+static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn)
+{
+ LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l);
+ check_r0_write(a->d);
+ tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
+ return true;
+}
+
+static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn)
+{
+ LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l);
+ check_r0_write(a->d);
+ tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
+ return true;
+}
+
+static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn)
+{
+ LOG_DIS("l.movhi r%d, %d\n", a->d, a->k);
+ check_r0_write(a->d);
+ tcg_gen_movi_tl(cpu_R[a->d], a->k << 16);
+ return true;
+}
+
+static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn)
+{
+ LOG_DIS("l.macrc r%d\n", a->d);
+ check_r0_write(a->d);
+ tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac);
+ tcg_gen_movi_i64(cpu_mac, 0);
+ return true;
+}
+
+static bool trans_l_sfeq(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sfeq r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_sfne(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sfne r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgtu r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgeu r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_sfltu(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sfltu r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_sfleu(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sfleu r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
- if (max_insns == 0) {
- max_insns = CF_COUNT_MASK;
+static bool trans_l_sfgts(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgts r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_sfges(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sfges r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_sflts(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sflts r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond)
+{
+ LOG_DIS("l.sfles r%d, r%d\n", a->a, a->b);
+ tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
+ return true;
+}
+
+static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfeqi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfnei r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgtui r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgeui r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfltui r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfleui r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgtsi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfgesi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sfltsi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond)
+{
+ LOG_DIS("l.sflesi r%d, %d\n", a->a, a->i);
+ tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i);
+ return true;
+}
+
+static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn)
+{
+ LOG_DIS("l.sys %d\n", a->k);
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
+ gen_exception(dc, EXCP_SYSCALL);
+ dc->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn)
+{
+ LOG_DIS("l.trap %d\n", a->k);
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
+ gen_exception(dc, EXCP_TRAP);
+ dc->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn)
+{
+ LOG_DIS("l.msync\n");
+ tcg_gen_mb(TCG_MO_ALL);
+ return true;
+}
+
+static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn)
+{
+ LOG_DIS("l.psync\n");
+ return true;
+}
+
+static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn)
+{
+ LOG_DIS("l.csync\n");
+ return true;
+}
+
+static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn)
+{
+ LOG_DIS("l.rfe\n");
+
+#ifdef CONFIG_USER_ONLY
+ gen_illegal_exception(dc);
+#else
+ if (dc->mem_idx == MMU_USER_IDX) {
+ gen_illegal_exception(dc);
+ } else {
+ gen_helper_rfe(cpu_env);
+ dc->base.is_jmp = DISAS_UPDATE;
+ }
+#endif
+ return true;
+}
+
+static void do_fp2(DisasContext *dc, arg_da *a,
+ void (*fn)(TCGv, TCGv_env, TCGv))
+{
+ check_r0_write(a->d);
+ fn(cpu_R[a->d], cpu_env, cpu_R[a->a]);
+ gen_helper_update_fpcsr(cpu_env);
+}
+
+static void do_fp3(DisasContext *dc, arg_dab *a,
+ void (*fn)(TCGv, TCGv_env, TCGv, TCGv))
+{
+ check_r0_write(a->d);
+ fn(cpu_R[a->d], cpu_env, cpu_R[a->a], cpu_R[a->b]);
+ gen_helper_update_fpcsr(cpu_env);
+}
+
+static void do_fpcmp(DisasContext *dc, arg_ab *a,
+ void (*fn)(TCGv, TCGv_env, TCGv, TCGv),
+ bool inv, bool swap)
+{
+ if (swap) {
+ fn(cpu_sr_f, cpu_env, cpu_R[a->b], cpu_R[a->a]);
+ } else {
+ fn(cpu_sr_f, cpu_env, cpu_R[a->a], cpu_R[a->b]);
}
- if (max_insns > TCG_MAX_INSNS) {
- max_insns = TCG_MAX_INSNS;
+ if (inv) {
+ tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
}
+ gen_helper_update_fpcsr(cpu_env);
+}
- gen_tb_start(tb);
+static bool trans_lf_add_s(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("lf.add.s r%d, r%d, r%d\n", a->d, a->a, a->b);
+ do_fp3(dc, a, gen_helper_float_add_s);
+ return true;
+}
- do {
- tcg_gen_insn_start(dc->pc);
- num_insns++;
+static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("lf.sub.s r%d, r%d, r%d\n", a->d, a->a, a->b);
+ do_fp3(dc, a, gen_helper_float_sub_s);
+ return true;
+}
- if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
- tcg_gen_movi_tl(cpu_pc, dc->pc);
- gen_exception(dc, EXCP_DEBUG);
- dc->is_jmp = DISAS_UPDATE;
- /* The address covered by the breakpoint must be included in
- [tb->pc, tb->pc + tb->size) in order to for it to be
- properly cleared -- thus we increment the PC here so that
- the logic setting tb->size below does the right thing. */
- dc->pc += 4;
- break;
- }
+static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("lf.mul.s r%d, r%d, r%d\n", a->d, a->a, a->b);
+ do_fp3(dc, a, gen_helper_float_mul_s);
+ return true;
+}
- if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
- gen_io_start();
- }
- dc->ppc = dc->pc - 4;
- dc->npc = dc->pc + 4;
- tcg_gen_movi_tl(cpu_ppc, dc->ppc);
- tcg_gen_movi_tl(cpu_npc, dc->npc);
- disas_openrisc_insn(dc, cpu);
- dc->pc = dc->npc;
- /* delay slot */
- if (dc->delayed_branch) {
- dc->delayed_branch--;
- if (!dc->delayed_branch) {
- dc->tb_flags &= ~D_FLAG;
- gen_sync_flags(dc);
- tcg_gen_mov_tl(cpu_pc, jmp_pc);
- tcg_gen_mov_tl(cpu_npc, jmp_pc);
- tcg_gen_movi_tl(jmp_pc, 0);
- tcg_gen_exit_tb(0);
- dc->is_jmp = DISAS_JUMP;
- break;
- }
- }
- } while (!dc->is_jmp
- && !tcg_op_buf_full()
- && !cs->singlestep_enabled
- && !singlestep
- && (dc->pc < next_page_start)
- && num_insns < max_insns);
-
- if (tb->cflags & CF_LAST_IO) {
- gen_io_end();
+static bool trans_lf_div_s(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("lf.div.s r%d, r%d, r%d\n", a->d, a->a, a->b);
+ do_fp3(dc, a, gen_helper_float_div_s);
+ return true;
+}
+
+static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("lf.rem.s r%d, r%d, r%d\n", a->d, a->a, a->b);
+ do_fp3(dc, a, gen_helper_float_rem_s);
+ return true;
+}
+
+static bool trans_lf_itof_s(DisasContext *dc, arg_da *a, uint32_t insn)
+{
+ LOG_DIS("lf.itof.s r%d, r%d\n", a->d, a->a);
+ do_fp2(dc, a, gen_helper_itofs);
+ return true;
+}
+
+static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a, uint32_t insn)
+{
+ LOG_DIS("lf.ftoi.s r%d, r%d\n", a->d, a->a);
+ do_fp2(dc, a, gen_helper_ftois);
+ return true;
+}
+
+static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn)
+{
+ LOG_DIS("lf.madd.s r%d, r%d, r%d\n", a->d, a->a, a->b);
+ check_r0_write(a->d);
+ gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d],
+ cpu_R[a->a], cpu_R[a->b]);
+ gen_helper_update_fpcsr(cpu_env);
+ return true;
+}
+
+static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("lf.sfeq.s r%d, r%d\n", a->a, a->b);
+ do_fpcmp(dc, a, gen_helper_float_eq_s, false, false);
+ return true;
+}
+
+static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("lf.sfne.s r%d, r%d\n", a->a, a->b);
+ do_fpcmp(dc, a, gen_helper_float_eq_s, true, false);
+ return true;
+}
+
+static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("lf.sfgt.s r%d, r%d\n", a->a, a->b);
+ do_fpcmp(dc, a, gen_helper_float_lt_s, false, true);
+ return true;
+}
+
+static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("lf.sfge.s r%d, r%d\n", a->a, a->b);
+ do_fpcmp(dc, a, gen_helper_float_le_s, false, true);
+ return true;
+}
+
+static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("lf.sflt.s r%d, r%d\n", a->a, a->b);
+ do_fpcmp(dc, a, gen_helper_float_lt_s, false, false);
+ return true;
+}
+
+static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn)
+{
+ LOG_DIS("lf.sfle.s r%d, r%d\n", a->a, a->b);
+ do_fpcmp(dc, a, gen_helper_float_le_s, false, false);
+ return true;
+}
+
+static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcb, DisasContext, base);
+ CPUOpenRISCState *env = cs->env_ptr;
+ int bound;
+
+ dc->mem_idx = cpu_mmu_index(env, false);
+ dc->tb_flags = dc->base.tb->flags;
+ dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
+ bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
+ dc->base.max_insns = MIN(dc->base.max_insns, bound);
+}
+
+static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs)
+{
+ DisasContext *dc = container_of(db, DisasContext, base);
+
+ /* Allow the TCG optimizer to see that R0 == 0,
+ when it's true, which is the common case. */
+ if (dc->tb_flags & TB_FLAGS_R0_0) {
+ cpu_R[0] = tcg_const_tl(0);
+ } else {
+ cpu_R[0] = cpu_R0;
}
- if (dc->is_jmp == DISAS_NEXT) {
- dc->is_jmp = DISAS_UPDATE;
- tcg_gen_movi_tl(cpu_pc, dc->pc);
+}
+
+static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
+ | (dc->base.num_insns > 1 ? 2 : 0));
+}
+
+static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
+ const CPUBreakpoint *bp)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
+ gen_exception(dc, EXCP_DEBUG);
+ dc->base.is_jmp = DISAS_NORETURN;
+ /* The address covered by the breakpoint must be included in
+ [tb->pc, tb->pc + tb->size) in order to for it to be
+ properly cleared -- thus we increment the PC here so that
+ the logic setting tb->size below does the right thing. */
+ dc->base.pc_next += 4;
+ return true;
+}
+
+static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+ uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next);
+
+ if (!decode(dc, insn)) {
+ gen_illegal_exception(dc);
}
- if (unlikely(cs->singlestep_enabled)) {
- if (dc->is_jmp == DISAS_NEXT) {
- tcg_gen_movi_tl(cpu_pc, dc->pc);
+ dc->base.pc_next += 4;
+
+ /* delay slot */
+ if (dc->delayed_branch) {
+ dc->delayed_branch--;
+ if (!dc->delayed_branch) {
+ tcg_gen_mov_tl(cpu_pc, jmp_pc);
+ tcg_gen_discard_tl(jmp_pc);
+ dc->base.is_jmp = DISAS_UPDATE;
+ return;
}
+ }
+}
+
+static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *dc = container_of(dcbase, DisasContext, base);
+
+ if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
+ tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
+ }
+
+ tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4);
+ if (dc->base.is_jmp == DISAS_NEXT) {
+ dc->base.is_jmp = DISAS_UPDATE;
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
+ }
+ if (unlikely(dc->base.singlestep_enabled)) {
gen_exception(dc, EXCP_DEBUG);
} else {
- switch (dc->is_jmp) {
- case DISAS_NEXT:
- gen_goto_tb(dc, 0, dc->pc);
+ switch (dc->base.is_jmp) {
+ case DISAS_TOO_MANY:
+ gen_goto_tb(dc, 0, dc->base.pc_next);
break;
- default:
+ case DISAS_NORETURN:
case DISAS_JUMP:
+ case DISAS_TB_JUMP:
break;
case DISAS_UPDATE:
/* indicate that the hash table must be used
to find the next TB */
tcg_gen_exit_tb(0);
break;
- case DISAS_TB_JUMP:
- /* nothing more to generate */
- break;
+ default:
+ g_assert_not_reached();
}
}
+}
- gen_tb_end(tb, num_insns);
-
- tb->size = dc->pc - pc_start;
- tb->icount = num_insns;
-
-#ifdef DEBUG_DISAS
- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
- && qemu_log_in_addr_range(pc_start)) {
- qemu_log_lock();
- qemu_log("----------------\n");
- qemu_log("IN: %s\n", lookup_symbol(pc_start));
- log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
- qemu_log("\nisize=%d osize=%d\n",
- dc->pc - pc_start, tcg_op_buf_count());
- qemu_log_unlock();
- }
-#endif
+static void openrisc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
+{
+ DisasContext *s = container_of(dcbase, DisasContext, base);
+
+ qemu_log("IN: %s\n", lookup_symbol(s->base.pc_first));
+ log_target_disas(cs, s->base.pc_first, s->base.tb->size);
+}
+
+static const TranslatorOps openrisc_tr_ops = {
+ .init_disas_context = openrisc_tr_init_disas_context,
+ .tb_start = openrisc_tr_tb_start,
+ .insn_start = openrisc_tr_insn_start,
+ .breakpoint_check = openrisc_tr_breakpoint_check,
+ .translate_insn = openrisc_tr_translate_insn,
+ .tb_stop = openrisc_tr_tb_stop,
+ .disas_log = openrisc_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
+{
+ DisasContext ctx;
+
+ translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb);
}
void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
cpu_fprintf(f, "PC=%08x\n", env->pc);
for (i = 0; i < 32; ++i) {
- cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i],
+ cpu_fprintf(f, "R%02d=%08x%c", i, cpu_get_gpr(env, i),
(i % 4) == 3 ? '\n' : ' ');
}
}
target_ulong *data)
{
env->pc = data[0];
+ env->dflag = data[1] & 1;
+ if (data[1] & 2) {
+ env->ppc = env->pc - 4;
+ }
}
projects / qemu.git / blobdiff