target/openrisc: Fix writes to interrupt mask register

[qemu.git] / target / openrisc / Makefile.objs

diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs
index 397d01650e838f61a74ff86ce40aaa1feaee2e27..b5432f46843ee40f1f66693a09416b9c0a7a4b88 100644 (file)
--- a/target/openrisc/Makefile.objs
+++ b/target/openrisc/Makefile.objs
@@ -1,5 +1,15 @@
 obj-$(CONFIG_SOFTMMU) += machine.o
-obj-y += cpu.o exception.o interrupt.o mmu.o translate.o
-obj-y += exception_helper.o fpu_helper.o int_helper.o \
-         interrupt_helper.o mmu_helper.o sys_helper.o
+obj-y += cpu.o exception.o interrupt.o mmu.o translate.o disas.o
+obj-y += exception_helper.o fpu_helper.o \
+         interrupt_helper.o sys_helper.o
 obj-y += gdbstub.o
+
+DECODETREE = $(SRC_PATH)/scripts/decodetree.py
+
+target/openrisc/decode.inc.c: \
+  $(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE)
+       $(call quiet-command,\
+         $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
+
+target/openrisc/translate.o: target/openrisc/decode.inc.c
+target/openrisc/disas.o: target/openrisc/decode.inc.c