target/openrisc: Fix writes to interrupt mask register

target/openrisc: Fix writes to interrupt mask register

The interrupt controller mask register (PICMR) allows writing any value
to any of the 32 interrupt mask bits.  Writing a 0 masks the interrupt
writing a 1 unmasks (enables) the the interrupt.

For some reason the old code was or'ing the write values to the PICMR
meaning it was not possible to ever mask a interrupt once it was
enabled.

I have tested this by running linux 4.18 and my regular checks, I don't
see any issues.

Reported-by: Davidson Francis <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Stafford Horne <[email protected]>