target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23 #include "hw/qdev-properties.h"
  24 #include "qapi/qmp/qerror.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31
  32 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  33 {
  34     ARMCPU *cpu = ARM_CPU(cs);
  35
  36     cpu->env.regs[15] = value;
  37 }
  38
  39 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  40 {
  41     /* Reset a single ARMCPRegInfo register */
  42     ARMCPRegInfo *ri = value;
  43     ARMCPU *cpu = opaque;
  44
  45     if (ri->type & ARM_CP_SPECIAL) {
  46         return;
  47     }
  48
  49     if (ri->resetfn) {
  50         ri->resetfn(&cpu->env, ri);
  51         return;
  52     }
  53
  54     /* A zero offset is never possible as it would be regs[0]
  55      * so we use it to indicate that reset is being handled elsewhere.
  56      * This is basically only used for fields in non-core coprocessors
  57      * (like the pxa2xx ones).
  58      */
  59     if (!ri->fieldoffset) {
  60         return;
  61     }
  62
  63     if (ri->type & ARM_CP_64BIT) {
  64         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  65     } else {
  66         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  67     }
  68 }
  69
  70 /* CPUClass::reset() */
  71 static void arm_cpu_reset(CPUState *s)
  72 {
  73     ARMCPU *cpu = ARM_CPU(s);
  74     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  75     CPUARMState *env = &cpu->env;
  76
  77     acc->parent_reset(s);
  78
  79     memset(env, 0, offsetof(CPUARMState, breakpoints));
  80     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  81     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  82     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  83     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  84
  85     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  86         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  87     }
  88
  89     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  90         /* 64 bit CPUs always start in 64 bit mode */
  91         env->aarch64 = 1;
  92 #if defined(CONFIG_USER_ONLY)
  93         env->pstate = PSTATE_MODE_EL0t;
  94 #else
  95         env->pstate = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F
  96             | PSTATE_MODE_EL1h;
  97 #endif
  98     }
  99
 100 #if defined(CONFIG_USER_ONLY)
 101     env->uncached_cpsr = ARM_CPU_MODE_USR;
 102     /* For user mode we must enable access to coprocessors */
 103     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 104     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 105         env->cp15.c15_cpar = 3;
 106     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 107         env->cp15.c15_cpar = 1;
 108     }
 109 #else
 110     /* SVC mode with interrupts disabled.  */
 111     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
 112     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 113        clear at reset.  Initial SP and PC are loaded from ROM.  */
 114     if (IS_M(env)) {
 115         uint32_t pc;
 116         uint8_t *rom;
 117         env->uncached_cpsr &= ~CPSR_I;
 118         rom = rom_ptr(0);
 119         if (rom) {
 120             /* We should really use ldl_phys here, in case the guest
 121                modified flash and reset itself.  However images
 122                loaded via -kernel have not been copied yet, so load the
 123                values directly from there.  */
 124             env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
 125             pc = ldl_p(rom + 4);
 126             env->thumb = pc & 1;
 127             env->regs[15] = pc & ~1;
 128         }
 129     }
 130
 131     if (env->cp15.c1_sys & (1 << 13)) {
 132             env->regs[15] = 0xFFFF0000;
 133     }
 134
 135     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 136 #endif
 137     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 138     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 139     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 140     set_float_detect_tininess(float_tininess_before_rounding,
 141                               &env->vfp.fp_status);
 142     set_float_detect_tininess(float_tininess_before_rounding,
 143                               &env->vfp.standard_fp_status);
 144     tlb_flush(env, 1);
 145     /* Reset is a state change for some CPUARMState fields which we
 146      * bake assumptions about into translated code, so we need to
 147      * tb_flush().
 148      */
 149     tb_flush(env);
 150 }
 151
 152 #ifndef CONFIG_USER_ONLY
 153 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 154 {
 155     ARMCPU *cpu = opaque;
 156     CPUState *cs = CPU(cpu);
 157
 158     switch (irq) {
 159     case ARM_CPU_IRQ:
 160         if (level) {
 161             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 162         } else {
 163             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 164         }
 165         break;
 166     case ARM_CPU_FIQ:
 167         if (level) {
 168             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 169         } else {
 170             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 171         }
 172         break;
 173     default:
 174         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 175     }
 176 }
 177
 178 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 179 {
 180 #ifdef CONFIG_KVM
 181     ARMCPU *cpu = opaque;
 182     CPUState *cs = CPU(cpu);
 183     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 184
 185     switch (irq) {
 186     case ARM_CPU_IRQ:
 187         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 188         break;
 189     case ARM_CPU_FIQ:
 190         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 191         break;
 192     default:
 193         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 194     }
 195     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 196     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 197 #endif
 198 }
 199 #endif
 200
 201 static inline void set_feature(CPUARMState *env, int feature)
 202 {
 203     env->features |= 1ULL << feature;
 204 }
 205
 206 static void arm_cpu_initfn(Object *obj)
 207 {
 208     CPUState *cs = CPU(obj);
 209     ARMCPU *cpu = ARM_CPU(obj);
 210     static bool inited;
 211
 212     cs->env_ptr = &cpu->env;
 213     cpu_exec_init(&cpu->env);
 214     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 215                                          g_free, g_free);
 216
 217 #ifndef CONFIG_USER_ONLY
 218     /* Our inbound IRQ and FIQ lines */
 219     if (kvm_enabled()) {
 220         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 221     } else {
 222         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 223     }
 224
 225     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 226                                                 arm_gt_ptimer_cb, cpu);
 227     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 228                                                 arm_gt_vtimer_cb, cpu);
 229     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 230                        ARRAY_SIZE(cpu->gt_timer_outputs));
 231 #endif
 232
 233     /* DTB consumers generally don't in fact care what the 'compatible'
 234      * string is, so always provide some string and trust that a hypothetical
 235      * picky DTB consumer will also provide a helpful error message.
 236      */
 237     cpu->dtb_compatible = "qemu,unknown";
 238     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 239
 240     if (tcg_enabled() && !inited) {
 241         inited = true;
 242         arm_translate_init();
 243     }
 244 }
 245
 246 static Property arm_cpu_reset_cbar_property =
 247             DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0);
 248
 249 static Property arm_cpu_reset_hivecs_property =
 250             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 251
 252 static void arm_cpu_post_init(Object *obj)
 253 {
 254     ARMCPU *cpu = ARM_CPU(obj);
 255
 256     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
 257         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 258                                  &error_abort);
 259     }
 260
 261     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 262         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 263                                  &error_abort);
 264     }
 265 }
 266
 267 static void arm_cpu_finalizefn(Object *obj)
 268 {
 269     ARMCPU *cpu = ARM_CPU(obj);
 270     g_hash_table_destroy(cpu->cp_regs);
 271 }
 272
 273 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 274 {
 275     CPUState *cs = CPU(dev);
 276     ARMCPU *cpu = ARM_CPU(dev);
 277     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 278     CPUARMState *env = &cpu->env;
 279
 280     /* Some features automatically imply others: */
 281     if (arm_feature(env, ARM_FEATURE_V8)) {
 282         set_feature(env, ARM_FEATURE_V7);
 283         set_feature(env, ARM_FEATURE_ARM_DIV);
 284         set_feature(env, ARM_FEATURE_LPAE);
 285         set_feature(env, ARM_FEATURE_V8_AES);
 286     }
 287     if (arm_feature(env, ARM_FEATURE_V7)) {
 288         set_feature(env, ARM_FEATURE_VAPA);
 289         set_feature(env, ARM_FEATURE_THUMB2);
 290         set_feature(env, ARM_FEATURE_MPIDR);
 291         if (!arm_feature(env, ARM_FEATURE_M)) {
 292             set_feature(env, ARM_FEATURE_V6K);
 293         } else {
 294             set_feature(env, ARM_FEATURE_V6);
 295         }
 296     }
 297     if (arm_feature(env, ARM_FEATURE_V6K)) {
 298         set_feature(env, ARM_FEATURE_V6);
 299         set_feature(env, ARM_FEATURE_MVFR);
 300     }
 301     if (arm_feature(env, ARM_FEATURE_V6)) {
 302         set_feature(env, ARM_FEATURE_V5);
 303         if (!arm_feature(env, ARM_FEATURE_M)) {
 304             set_feature(env, ARM_FEATURE_AUXCR);
 305         }
 306     }
 307     if (arm_feature(env, ARM_FEATURE_V5)) {
 308         set_feature(env, ARM_FEATURE_V4T);
 309     }
 310     if (arm_feature(env, ARM_FEATURE_M)) {
 311         set_feature(env, ARM_FEATURE_THUMB_DIV);
 312     }
 313     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 314         set_feature(env, ARM_FEATURE_THUMB_DIV);
 315     }
 316     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 317         set_feature(env, ARM_FEATURE_VFP3);
 318     }
 319     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 320         set_feature(env, ARM_FEATURE_VFP);
 321     }
 322     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 323         set_feature(env, ARM_FEATURE_V7MP);
 324         set_feature(env, ARM_FEATURE_PXN);
 325     }
 326
 327     if (cpu->reset_hivecs) {
 328             cpu->reset_sctlr |= (1 << 13);
 329     }
 330
 331     register_cp_regs_for_features(cpu);
 332     arm_cpu_register_gdb_regs_for_features(cpu);
 333
 334     init_cpreg_list(cpu);
 335
 336     cpu_reset(cs);
 337     qemu_init_vcpu(cs);
 338
 339     acc->parent_realize(dev, errp);
 340 }
 341
 342 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 343 {
 344     ObjectClass *oc;
 345     char *typename;
 346
 347     if (!cpu_model) {
 348         return NULL;
 349     }
 350
 351     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 352     oc = object_class_by_name(typename);
 353     g_free(typename);
 354     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 355         object_class_is_abstract(oc)) {
 356         return NULL;
 357     }
 358     return oc;
 359 }
 360
 361 /* CPU models. These are not needed for the AArch64 linux-user build. */
 362 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 363
 364 static void arm926_initfn(Object *obj)
 365 {
 366     ARMCPU *cpu = ARM_CPU(obj);
 367
 368     cpu->dtb_compatible = "arm,arm926";
 369     set_feature(&cpu->env, ARM_FEATURE_V5);
 370     set_feature(&cpu->env, ARM_FEATURE_VFP);
 371     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 372     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 373     cpu->midr = 0x41069265;
 374     cpu->reset_fpsid = 0x41011090;
 375     cpu->ctr = 0x1dd20d2;
 376     cpu->reset_sctlr = 0x00090078;
 377 }
 378
 379 static void arm946_initfn(Object *obj)
 380 {
 381     ARMCPU *cpu = ARM_CPU(obj);
 382
 383     cpu->dtb_compatible = "arm,arm946";
 384     set_feature(&cpu->env, ARM_FEATURE_V5);
 385     set_feature(&cpu->env, ARM_FEATURE_MPU);
 386     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 387     cpu->midr = 0x41059461;
 388     cpu->ctr = 0x0f004006;
 389     cpu->reset_sctlr = 0x00000078;
 390 }
 391
 392 static void arm1026_initfn(Object *obj)
 393 {
 394     ARMCPU *cpu = ARM_CPU(obj);
 395
 396     cpu->dtb_compatible = "arm,arm1026";
 397     set_feature(&cpu->env, ARM_FEATURE_V5);
 398     set_feature(&cpu->env, ARM_FEATURE_VFP);
 399     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 400     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 401     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 402     cpu->midr = 0x4106a262;
 403     cpu->reset_fpsid = 0x410110a0;
 404     cpu->ctr = 0x1dd20d2;
 405     cpu->reset_sctlr = 0x00090078;
 406     cpu->reset_auxcr = 1;
 407     {
 408         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 409         ARMCPRegInfo ifar = {
 410             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 411             .access = PL1_RW,
 412             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 413             .resetvalue = 0
 414         };
 415         define_one_arm_cp_reg(cpu, &ifar);
 416     }
 417 }
 418
 419 static void arm1136_r2_initfn(Object *obj)
 420 {
 421     ARMCPU *cpu = ARM_CPU(obj);
 422     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 423      * older core than plain "arm1136". In particular this does not
 424      * have the v6K features.
 425      * These ID register values are correct for 1136 but may be wrong
 426      * for 1136_r2 (in particular r0p2 does not actually implement most
 427      * of the ID registers).
 428      */
 429
 430     cpu->dtb_compatible = "arm,arm1136";
 431     set_feature(&cpu->env, ARM_FEATURE_V6);
 432     set_feature(&cpu->env, ARM_FEATURE_VFP);
 433     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 434     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 435     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 436     cpu->midr = 0x4107b362;
 437     cpu->reset_fpsid = 0x410120b4;
 438     cpu->mvfr0 = 0x11111111;
 439     cpu->mvfr1 = 0x00000000;
 440     cpu->ctr = 0x1dd20d2;
 441     cpu->reset_sctlr = 0x00050078;
 442     cpu->id_pfr0 = 0x111;
 443     cpu->id_pfr1 = 0x1;
 444     cpu->id_dfr0 = 0x2;
 445     cpu->id_afr0 = 0x3;
 446     cpu->id_mmfr0 = 0x01130003;
 447     cpu->id_mmfr1 = 0x10030302;
 448     cpu->id_mmfr2 = 0x01222110;
 449     cpu->id_isar0 = 0x00140011;
 450     cpu->id_isar1 = 0x12002111;
 451     cpu->id_isar2 = 0x11231111;
 452     cpu->id_isar3 = 0x01102131;
 453     cpu->id_isar4 = 0x141;
 454     cpu->reset_auxcr = 7;
 455 }
 456
 457 static void arm1136_initfn(Object *obj)
 458 {
 459     ARMCPU *cpu = ARM_CPU(obj);
 460
 461     cpu->dtb_compatible = "arm,arm1136";
 462     set_feature(&cpu->env, ARM_FEATURE_V6K);
 463     set_feature(&cpu->env, ARM_FEATURE_V6);
 464     set_feature(&cpu->env, ARM_FEATURE_VFP);
 465     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 466     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 467     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 468     cpu->midr = 0x4117b363;
 469     cpu->reset_fpsid = 0x410120b4;
 470     cpu->mvfr0 = 0x11111111;
 471     cpu->mvfr1 = 0x00000000;
 472     cpu->ctr = 0x1dd20d2;
 473     cpu->reset_sctlr = 0x00050078;
 474     cpu->id_pfr0 = 0x111;
 475     cpu->id_pfr1 = 0x1;
 476     cpu->id_dfr0 = 0x2;
 477     cpu->id_afr0 = 0x3;
 478     cpu->id_mmfr0 = 0x01130003;
 479     cpu->id_mmfr1 = 0x10030302;
 480     cpu->id_mmfr2 = 0x01222110;
 481     cpu->id_isar0 = 0x00140011;
 482     cpu->id_isar1 = 0x12002111;
 483     cpu->id_isar2 = 0x11231111;
 484     cpu->id_isar3 = 0x01102131;
 485     cpu->id_isar4 = 0x141;
 486     cpu->reset_auxcr = 7;
 487 }
 488
 489 static void arm1176_initfn(Object *obj)
 490 {
 491     ARMCPU *cpu = ARM_CPU(obj);
 492
 493     cpu->dtb_compatible = "arm,arm1176";
 494     set_feature(&cpu->env, ARM_FEATURE_V6K);
 495     set_feature(&cpu->env, ARM_FEATURE_VFP);
 496     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 497     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 498     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 499     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 500     cpu->midr = 0x410fb767;
 501     cpu->reset_fpsid = 0x410120b5;
 502     cpu->mvfr0 = 0x11111111;
 503     cpu->mvfr1 = 0x00000000;
 504     cpu->ctr = 0x1dd20d2;
 505     cpu->reset_sctlr = 0x00050078;
 506     cpu->id_pfr0 = 0x111;
 507     cpu->id_pfr1 = 0x11;
 508     cpu->id_dfr0 = 0x33;
 509     cpu->id_afr0 = 0;
 510     cpu->id_mmfr0 = 0x01130003;
 511     cpu->id_mmfr1 = 0x10030302;
 512     cpu->id_mmfr2 = 0x01222100;
 513     cpu->id_isar0 = 0x0140011;
 514     cpu->id_isar1 = 0x12002111;
 515     cpu->id_isar2 = 0x11231121;
 516     cpu->id_isar3 = 0x01102131;
 517     cpu->id_isar4 = 0x01141;
 518     cpu->reset_auxcr = 7;
 519 }
 520
 521 static void arm11mpcore_initfn(Object *obj)
 522 {
 523     ARMCPU *cpu = ARM_CPU(obj);
 524
 525     cpu->dtb_compatible = "arm,arm11mpcore";
 526     set_feature(&cpu->env, ARM_FEATURE_V6K);
 527     set_feature(&cpu->env, ARM_FEATURE_VFP);
 528     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 529     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 530     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 531     cpu->midr = 0x410fb022;
 532     cpu->reset_fpsid = 0x410120b4;
 533     cpu->mvfr0 = 0x11111111;
 534     cpu->mvfr1 = 0x00000000;
 535     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 536     cpu->id_pfr0 = 0x111;
 537     cpu->id_pfr1 = 0x1;
 538     cpu->id_dfr0 = 0;
 539     cpu->id_afr0 = 0x2;
 540     cpu->id_mmfr0 = 0x01100103;
 541     cpu->id_mmfr1 = 0x10020302;
 542     cpu->id_mmfr2 = 0x01222000;
 543     cpu->id_isar0 = 0x00100011;
 544     cpu->id_isar1 = 0x12002111;
 545     cpu->id_isar2 = 0x11221011;
 546     cpu->id_isar3 = 0x01102131;
 547     cpu->id_isar4 = 0x141;
 548     cpu->reset_auxcr = 1;
 549 }
 550
 551 static void cortex_m3_initfn(Object *obj)
 552 {
 553     ARMCPU *cpu = ARM_CPU(obj);
 554     set_feature(&cpu->env, ARM_FEATURE_V7);
 555     set_feature(&cpu->env, ARM_FEATURE_M);
 556     cpu->midr = 0x410fc231;
 557 }
 558
 559 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 560 {
 561 #ifndef CONFIG_USER_ONLY
 562     CPUClass *cc = CPU_CLASS(oc);
 563
 564     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 565 #endif
 566 }
 567
 568 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 569     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 570       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 571     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 572       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 573     REGINFO_SENTINEL
 574 };
 575
 576 static void cortex_a8_initfn(Object *obj)
 577 {
 578     ARMCPU *cpu = ARM_CPU(obj);
 579
 580     cpu->dtb_compatible = "arm,cortex-a8";
 581     set_feature(&cpu->env, ARM_FEATURE_V7);
 582     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 583     set_feature(&cpu->env, ARM_FEATURE_NEON);
 584     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 585     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 586     cpu->midr = 0x410fc080;
 587     cpu->reset_fpsid = 0x410330c0;
 588     cpu->mvfr0 = 0x11110222;
 589     cpu->mvfr1 = 0x00011100;
 590     cpu->ctr = 0x82048004;
 591     cpu->reset_sctlr = 0x00c50078;
 592     cpu->id_pfr0 = 0x1031;
 593     cpu->id_pfr1 = 0x11;
 594     cpu->id_dfr0 = 0x400;
 595     cpu->id_afr0 = 0;
 596     cpu->id_mmfr0 = 0x31100003;
 597     cpu->id_mmfr1 = 0x20000000;
 598     cpu->id_mmfr2 = 0x01202000;
 599     cpu->id_mmfr3 = 0x11;
 600     cpu->id_isar0 = 0x00101111;
 601     cpu->id_isar1 = 0x12112111;
 602     cpu->id_isar2 = 0x21232031;
 603     cpu->id_isar3 = 0x11112131;
 604     cpu->id_isar4 = 0x00111142;
 605     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 606     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 607     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 608     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 609     cpu->reset_auxcr = 2;
 610     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 611 }
 612
 613 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 614     /* power_control should be set to maximum latency. Again,
 615      * default to 0 and set by private hook
 616      */
 617     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 618       .access = PL1_RW, .resetvalue = 0,
 619       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 620     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 621       .access = PL1_RW, .resetvalue = 0,
 622       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 623     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 624       .access = PL1_RW, .resetvalue = 0,
 625       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 626     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 627       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 628     /* TLB lockdown control */
 629     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 630       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 631     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 632       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 633     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 634       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 635     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 636       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 637     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 638       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 639     REGINFO_SENTINEL
 640 };
 641
 642 static void cortex_a9_initfn(Object *obj)
 643 {
 644     ARMCPU *cpu = ARM_CPU(obj);
 645
 646     cpu->dtb_compatible = "arm,cortex-a9";
 647     set_feature(&cpu->env, ARM_FEATURE_V7);
 648     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 649     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 650     set_feature(&cpu->env, ARM_FEATURE_NEON);
 651     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 652     /* Note that A9 supports the MP extensions even for
 653      * A9UP and single-core A9MP (which are both different
 654      * and valid configurations; we don't model A9UP).
 655      */
 656     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 657     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 658     cpu->midr = 0x410fc090;
 659     cpu->reset_fpsid = 0x41033090;
 660     cpu->mvfr0 = 0x11110222;
 661     cpu->mvfr1 = 0x01111111;
 662     cpu->ctr = 0x80038003;
 663     cpu->reset_sctlr = 0x00c50078;
 664     cpu->id_pfr0 = 0x1031;
 665     cpu->id_pfr1 = 0x11;
 666     cpu->id_dfr0 = 0x000;
 667     cpu->id_afr0 = 0;
 668     cpu->id_mmfr0 = 0x00100103;
 669     cpu->id_mmfr1 = 0x20000000;
 670     cpu->id_mmfr2 = 0x01230000;
 671     cpu->id_mmfr3 = 0x00002111;
 672     cpu->id_isar0 = 0x00101111;
 673     cpu->id_isar1 = 0x13112111;
 674     cpu->id_isar2 = 0x21232041;
 675     cpu->id_isar3 = 0x11112131;
 676     cpu->id_isar4 = 0x00111142;
 677     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 678     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 679     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 680     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 681 }
 682
 683 #ifndef CONFIG_USER_ONLY
 684 static int a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri,
 685                            uint64_t *value)
 686 {
 687     /* Linux wants the number of processors from here.
 688      * Might as well set the interrupt-controller bit too.
 689      */
 690     *value = ((smp_cpus - 1) << 24) | (1 << 23);
 691     return 0;
 692 }
 693 #endif
 694
 695 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 696 #ifndef CONFIG_USER_ONLY
 697     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 698       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 699       .writefn = arm_cp_write_ignore, },
 700 #endif
 701     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 702       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 703     REGINFO_SENTINEL
 704 };
 705
 706 static void cortex_a15_initfn(Object *obj)
 707 {
 708     ARMCPU *cpu = ARM_CPU(obj);
 709
 710     cpu->dtb_compatible = "arm,cortex-a15";
 711     set_feature(&cpu->env, ARM_FEATURE_V7);
 712     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 713     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 714     set_feature(&cpu->env, ARM_FEATURE_NEON);
 715     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 716     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 717     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 718     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 719     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 720     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 721     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 722     cpu->midr = 0x412fc0f1;
 723     cpu->reset_fpsid = 0x410430f0;
 724     cpu->mvfr0 = 0x10110222;
 725     cpu->mvfr1 = 0x11111111;
 726     cpu->ctr = 0x8444c004;
 727     cpu->reset_sctlr = 0x00c50078;
 728     cpu->id_pfr0 = 0x00001131;
 729     cpu->id_pfr1 = 0x00011011;
 730     cpu->id_dfr0 = 0x02010555;
 731     cpu->id_afr0 = 0x00000000;
 732     cpu->id_mmfr0 = 0x10201105;
 733     cpu->id_mmfr1 = 0x20000000;
 734     cpu->id_mmfr2 = 0x01240000;
 735     cpu->id_mmfr3 = 0x02102211;
 736     cpu->id_isar0 = 0x02101110;
 737     cpu->id_isar1 = 0x13112111;
 738     cpu->id_isar2 = 0x21232041;
 739     cpu->id_isar3 = 0x11112131;
 740     cpu->id_isar4 = 0x10011142;
 741     cpu->clidr = 0x0a200023;
 742     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 743     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 744     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 745     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 746 }
 747
 748 static void ti925t_initfn(Object *obj)
 749 {
 750     ARMCPU *cpu = ARM_CPU(obj);
 751     set_feature(&cpu->env, ARM_FEATURE_V4T);
 752     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 753     cpu->midr = ARM_CPUID_TI925T;
 754     cpu->ctr = 0x5109149;
 755     cpu->reset_sctlr = 0x00000070;
 756 }
 757
 758 static void sa1100_initfn(Object *obj)
 759 {
 760     ARMCPU *cpu = ARM_CPU(obj);
 761
 762     cpu->dtb_compatible = "intel,sa1100";
 763     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 764     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 765     cpu->midr = 0x4401A11B;
 766     cpu->reset_sctlr = 0x00000070;
 767 }
 768
 769 static void sa1110_initfn(Object *obj)
 770 {
 771     ARMCPU *cpu = ARM_CPU(obj);
 772     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 773     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 774     cpu->midr = 0x6901B119;
 775     cpu->reset_sctlr = 0x00000070;
 776 }
 777
 778 static void pxa250_initfn(Object *obj)
 779 {
 780     ARMCPU *cpu = ARM_CPU(obj);
 781
 782     cpu->dtb_compatible = "marvell,xscale";
 783     set_feature(&cpu->env, ARM_FEATURE_V5);
 784     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 785     cpu->midr = 0x69052100;
 786     cpu->ctr = 0xd172172;
 787     cpu->reset_sctlr = 0x00000078;
 788 }
 789
 790 static void pxa255_initfn(Object *obj)
 791 {
 792     ARMCPU *cpu = ARM_CPU(obj);
 793
 794     cpu->dtb_compatible = "marvell,xscale";
 795     set_feature(&cpu->env, ARM_FEATURE_V5);
 796     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 797     cpu->midr = 0x69052d00;
 798     cpu->ctr = 0xd172172;
 799     cpu->reset_sctlr = 0x00000078;
 800 }
 801
 802 static void pxa260_initfn(Object *obj)
 803 {
 804     ARMCPU *cpu = ARM_CPU(obj);
 805
 806     cpu->dtb_compatible = "marvell,xscale";
 807     set_feature(&cpu->env, ARM_FEATURE_V5);
 808     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 809     cpu->midr = 0x69052903;
 810     cpu->ctr = 0xd172172;
 811     cpu->reset_sctlr = 0x00000078;
 812 }
 813
 814 static void pxa261_initfn(Object *obj)
 815 {
 816     ARMCPU *cpu = ARM_CPU(obj);
 817
 818     cpu->dtb_compatible = "marvell,xscale";
 819     set_feature(&cpu->env, ARM_FEATURE_V5);
 820     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 821     cpu->midr = 0x69052d05;
 822     cpu->ctr = 0xd172172;
 823     cpu->reset_sctlr = 0x00000078;
 824 }
 825
 826 static void pxa262_initfn(Object *obj)
 827 {
 828     ARMCPU *cpu = ARM_CPU(obj);
 829
 830     cpu->dtb_compatible = "marvell,xscale";
 831     set_feature(&cpu->env, ARM_FEATURE_V5);
 832     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 833     cpu->midr = 0x69052d06;
 834     cpu->ctr = 0xd172172;
 835     cpu->reset_sctlr = 0x00000078;
 836 }
 837
 838 static void pxa270a0_initfn(Object *obj)
 839 {
 840     ARMCPU *cpu = ARM_CPU(obj);
 841
 842     cpu->dtb_compatible = "marvell,xscale";
 843     set_feature(&cpu->env, ARM_FEATURE_V5);
 844     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 845     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 846     cpu->midr = 0x69054110;
 847     cpu->ctr = 0xd172172;
 848     cpu->reset_sctlr = 0x00000078;
 849 }
 850
 851 static void pxa270a1_initfn(Object *obj)
 852 {
 853     ARMCPU *cpu = ARM_CPU(obj);
 854
 855     cpu->dtb_compatible = "marvell,xscale";
 856     set_feature(&cpu->env, ARM_FEATURE_V5);
 857     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 858     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 859     cpu->midr = 0x69054111;
 860     cpu->ctr = 0xd172172;
 861     cpu->reset_sctlr = 0x00000078;
 862 }
 863
 864 static void pxa270b0_initfn(Object *obj)
 865 {
 866     ARMCPU *cpu = ARM_CPU(obj);
 867
 868     cpu->dtb_compatible = "marvell,xscale";
 869     set_feature(&cpu->env, ARM_FEATURE_V5);
 870     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 871     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 872     cpu->midr = 0x69054112;
 873     cpu->ctr = 0xd172172;
 874     cpu->reset_sctlr = 0x00000078;
 875 }
 876
 877 static void pxa270b1_initfn(Object *obj)
 878 {
 879     ARMCPU *cpu = ARM_CPU(obj);
 880
 881     cpu->dtb_compatible = "marvell,xscale";
 882     set_feature(&cpu->env, ARM_FEATURE_V5);
 883     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 884     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 885     cpu->midr = 0x69054113;
 886     cpu->ctr = 0xd172172;
 887     cpu->reset_sctlr = 0x00000078;
 888 }
 889
 890 static void pxa270c0_initfn(Object *obj)
 891 {
 892     ARMCPU *cpu = ARM_CPU(obj);
 893
 894     cpu->dtb_compatible = "marvell,xscale";
 895     set_feature(&cpu->env, ARM_FEATURE_V5);
 896     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 897     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 898     cpu->midr = 0x69054114;
 899     cpu->ctr = 0xd172172;
 900     cpu->reset_sctlr = 0x00000078;
 901 }
 902
 903 static void pxa270c5_initfn(Object *obj)
 904 {
 905     ARMCPU *cpu = ARM_CPU(obj);
 906
 907     cpu->dtb_compatible = "marvell,xscale";
 908     set_feature(&cpu->env, ARM_FEATURE_V5);
 909     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 910     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 911     cpu->midr = 0x69054117;
 912     cpu->ctr = 0xd172172;
 913     cpu->reset_sctlr = 0x00000078;
 914 }
 915
 916 #ifdef CONFIG_USER_ONLY
 917 static void arm_any_initfn(Object *obj)
 918 {
 919     ARMCPU *cpu = ARM_CPU(obj);
 920     set_feature(&cpu->env, ARM_FEATURE_V8);
 921     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 922     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 923     set_feature(&cpu->env, ARM_FEATURE_NEON);
 924     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 925     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 926     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 927 #ifdef TARGET_AARCH64
 928     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 929 #endif
 930     cpu->midr = 0xffffffff;
 931 }
 932 #endif
 933
 934 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 935
 936 typedef struct ARMCPUInfo {
 937     const char *name;
 938     void (*initfn)(Object *obj);
 939     void (*class_init)(ObjectClass *oc, void *data);
 940 } ARMCPUInfo;
 941
 942 static const ARMCPUInfo arm_cpus[] = {
 943 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 944     { .name = "arm926",      .initfn = arm926_initfn },
 945     { .name = "arm946",      .initfn = arm946_initfn },
 946     { .name = "arm1026",     .initfn = arm1026_initfn },
 947     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 948      * older core than plain "arm1136". In particular this does not
 949      * have the v6K features.
 950      */
 951     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 952     { .name = "arm1136",     .initfn = arm1136_initfn },
 953     { .name = "arm1176",     .initfn = arm1176_initfn },
 954     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 955     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 956                              .class_init = arm_v7m_class_init },
 957     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 958     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 959     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 960     { .name = "ti925t",      .initfn = ti925t_initfn },
 961     { .name = "sa1100",      .initfn = sa1100_initfn },
 962     { .name = "sa1110",      .initfn = sa1110_initfn },
 963     { .name = "pxa250",      .initfn = pxa250_initfn },
 964     { .name = "pxa255",      .initfn = pxa255_initfn },
 965     { .name = "pxa260",      .initfn = pxa260_initfn },
 966     { .name = "pxa261",      .initfn = pxa261_initfn },
 967     { .name = "pxa262",      .initfn = pxa262_initfn },
 968     /* "pxa270" is an alias for "pxa270-a0" */
 969     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 970     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 971     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 972     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 973     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 974     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 975     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 976 #ifdef CONFIG_USER_ONLY
 977     { .name = "any",         .initfn = arm_any_initfn },
 978 #endif
 979 #endif
 980     { .name = NULL }
 981 };
 982
 983 static Property arm_cpu_properties[] = {
 984     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
 985     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
 986     DEFINE_PROP_END_OF_LIST()
 987 };
 988
 989 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 990 {
 991     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 992     CPUClass *cc = CPU_CLASS(acc);
 993     DeviceClass *dc = DEVICE_CLASS(oc);
 994
 995     acc->parent_realize = dc->realize;
 996     dc->realize = arm_cpu_realizefn;
 997     dc->props = arm_cpu_properties;
 998
 999     acc->parent_reset = cc->reset;
1000     cc->reset = arm_cpu_reset;
1001
1002     cc->class_by_name = arm_cpu_class_by_name;
1003     cc->do_interrupt = arm_cpu_do_interrupt;
1004     cc->dump_state = arm_cpu_dump_state;
1005     cc->set_pc = arm_cpu_set_pc;
1006     cc->gdb_read_register = arm_cpu_gdb_read_register;
1007     cc->gdb_write_register = arm_cpu_gdb_write_register;
1008 #ifndef CONFIG_USER_ONLY
1009     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1010     cc->vmsd = &vmstate_arm_cpu;
1011 #endif
1012     cc->gdb_num_core_regs = 26;
1013     cc->gdb_core_xml_file = "arm-core.xml";
1014 }
1015
1016 static void cpu_register(const ARMCPUInfo *info)
1017 {
1018     TypeInfo type_info = {
1019         .parent = TYPE_ARM_CPU,
1020         .instance_size = sizeof(ARMCPU),
1021         .instance_init = info->initfn,
1022         .class_size = sizeof(ARMCPUClass),
1023         .class_init = info->class_init,
1024     };
1025
1026     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1027     type_register(&type_info);
1028     g_free((void *)type_info.name);
1029 }
1030
1031 static const TypeInfo arm_cpu_type_info = {
1032     .name = TYPE_ARM_CPU,
1033     .parent = TYPE_CPU,
1034     .instance_size = sizeof(ARMCPU),
1035     .instance_init = arm_cpu_initfn,
1036     .instance_post_init = arm_cpu_post_init,
1037     .instance_finalize = arm_cpu_finalizefn,
1038     .abstract = true,
1039     .class_size = sizeof(ARMCPUClass),
1040     .class_init = arm_cpu_class_init,
1041 };
1042
1043 static void arm_cpu_register_types(void)
1044 {
1045     const ARMCPUInfo *info = arm_cpus;
1046
1047     type_register_static(&arm_cpu_type_info);
1048
1049     while (info->name) {
1050         cpu_register(info);
1051         info++;
1052     }
1053 }
1054
1055 type_init(arm_cpu_register_types)