hw/arm/virt.c

   1 /*
   2  * ARM mach-virt emulation
   3  *
   4  * Copyright (c) 2013 Linaro Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Emulate a virtual board which works by passing Linux all the information
  19  * it needs about what devices are present via the device tree.
  20  * There are some restrictions about what we can do here:
  21  *  + we can only present devices whose Linux drivers will work based
  22  *    purely on the device tree with no platform data at all
  23  *  + we want to present a very stripped-down minimalist platform,
  24  *    both because this reduces the security attack surface from the guest
  25  *    and also because it reduces our exposure to being broken when
  26  *    the kernel updates its device tree bindings and requires further
  27  *    information in a device binding that we aren't providing.
  28  * This is essentially the same approach kvmtool uses.
  29  */
  30
  31 #include "qemu/osdep.h"
  32 #include "qemu-common.h"
  33 #include "qemu/datadir.h"
  34 #include "qemu/units.h"
  35 #include "qemu/option.h"
  36 #include "monitor/qdev.h"
  37 #include "qapi/error.h"
  38 #include "hw/sysbus.h"
  39 #include "hw/arm/boot.h"
  40 #include "hw/arm/primecell.h"
  41 #include "hw/arm/virt.h"
  42 #include "hw/block/flash.h"
  43 #include "hw/vfio/vfio-calxeda-xgmac.h"
  44 #include "hw/vfio/vfio-amd-xgbe.h"
  45 #include "hw/display/ramfb.h"
  46 #include "net/net.h"
  47 #include "sysemu/device_tree.h"
  48 #include "sysemu/numa.h"
  49 #include "sysemu/runstate.h"
  50 #include "sysemu/tpm.h"
  51 #include "sysemu/kvm.h"
  52 #include "hw/loader.h"
  53 #include "exec/address-spaces.h"
  54 #include "qemu/bitops.h"
  55 #include "qemu/error-report.h"
  56 #include "qemu/module.h"
  57 #include "hw/pci-host/gpex.h"
  58 #include "hw/virtio/virtio-pci.h"
  59 #include "hw/arm/sysbus-fdt.h"
  60 #include "hw/platform-bus.h"
  61 #include "hw/qdev-properties.h"
  62 #include "hw/arm/fdt.h"
  63 #include "hw/intc/arm_gic.h"
  64 #include "hw/intc/arm_gicv3_common.h"
  65 #include "hw/irq.h"
  66 #include "kvm_arm.h"
  67 #include "hw/firmware/smbios.h"
  68 #include "qapi/visitor.h"
  69 #include "qapi/qapi-visit-common.h"
  70 #include "standard-headers/linux/input.h"
  71 #include "hw/arm/smmuv3.h"
  72 #include "hw/acpi/acpi.h"
  73 #include "target/arm/internals.h"
  74 #include "hw/mem/pc-dimm.h"
  75 #include "hw/mem/nvdimm.h"
  76 #include "hw/acpi/generic_event_device.h"
  77 #include "hw/virtio/virtio-iommu.h"
  78 #include "hw/char/pl011.h"
  79 #include "qemu/guest-random.h"
  80
  81 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
  82     static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
  83                                                     void *data) \
  84     { \
  85         MachineClass *mc = MACHINE_CLASS(oc); \
  86         virt_machine_##major##_##minor##_options(mc); \
  87         mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
  88         if (latest) { \
  89             mc->alias = "virt"; \
  90         } \
  91     } \
  92     static const TypeInfo machvirt_##major##_##minor##_info = { \
  93         .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
  94         .parent = TYPE_VIRT_MACHINE, \
  95         .class_init = virt_##major##_##minor##_class_init, \
  96     }; \
  97     static void machvirt_machine_##major##_##minor##_init(void) \
  98     { \
  99         type_register_static(&machvirt_##major##_##minor##_info); \
 100     } \
 101     type_init(machvirt_machine_##major##_##minor##_init);
 102
 103 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
 104     DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
 105 #define DEFINE_VIRT_MACHINE(major, minor) \
 106     DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
 107
 108
 109 /* Number of external interrupt lines to configure the GIC with */
 110 #define NUM_IRQS 256
 111
 112 #define PLATFORM_BUS_NUM_IRQS 64
 113
 114 /* Legacy RAM limit in GB (< version 4.0) */
 115 #define LEGACY_RAMLIMIT_GB 255
 116 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
 117
 118 /* Addresses and sizes of our components.
 119  * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
 120  * 128MB..256MB is used for miscellaneous device I/O.
 121  * 256MB..1GB is reserved for possible future PCI support (ie where the
 122  * PCI memory window will go if we add a PCI host controller).
 123  * 1GB and up is RAM (which may happily spill over into the
 124  * high memory region beyond 4GB).
 125  * This represents a compromise between how much RAM can be given to
 126  * a 32 bit VM and leaving space for expansion and in particular for PCI.
 127  * Note that devices should generally be placed at multiples of 0x10000,
 128  * to accommodate guests using 64K pages.
 129  */
 130 static const MemMapEntry base_memmap[] = {
 131     /* Space up to 0x8000000 is reserved for a boot ROM */
 132     [VIRT_FLASH] =              {          0, 0x08000000 },
 133     [VIRT_CPUPERIPHS] =         { 0x08000000, 0x00020000 },
 134     /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
 135     [VIRT_GIC_DIST] =           { 0x08000000, 0x00010000 },
 136     [VIRT_GIC_CPU] =            { 0x08010000, 0x00010000 },
 137     [VIRT_GIC_V2M] =            { 0x08020000, 0x00001000 },
 138     [VIRT_GIC_HYP] =            { 0x08030000, 0x00010000 },
 139     [VIRT_GIC_VCPU] =           { 0x08040000, 0x00010000 },
 140     /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
 141     [VIRT_GIC_ITS] =            { 0x08080000, 0x00020000 },
 142     /* This redistributor space allows up to 2*64kB*123 CPUs */
 143     [VIRT_GIC_REDIST] =         { 0x080A0000, 0x00F60000 },
 144     [VIRT_UART] =               { 0x09000000, 0x00001000 },
 145     [VIRT_RTC] =                { 0x09010000, 0x00001000 },
 146     [VIRT_FW_CFG] =             { 0x09020000, 0x00000018 },
 147     [VIRT_GPIO] =               { 0x09030000, 0x00001000 },
 148     [VIRT_SECURE_UART] =        { 0x09040000, 0x00001000 },
 149     [VIRT_SMMU] =               { 0x09050000, 0x00020000 },
 150     [VIRT_PCDIMM_ACPI] =        { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
 151     [VIRT_ACPI_GED] =           { 0x09080000, ACPI_GED_EVT_SEL_LEN },
 152     [VIRT_NVDIMM_ACPI] =        { 0x09090000, NVDIMM_ACPI_IO_LEN},
 153     [VIRT_PVTIME] =             { 0x090a0000, 0x00010000 },
 154     [VIRT_SECURE_GPIO] =        { 0x090b0000, 0x00001000 },
 155     [VIRT_MMIO] =               { 0x0a000000, 0x00000200 },
 156     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
 157     [VIRT_PLATFORM_BUS] =       { 0x0c000000, 0x02000000 },
 158     [VIRT_SECURE_MEM] =         { 0x0e000000, 0x01000000 },
 159     [VIRT_PCIE_MMIO] =          { 0x10000000, 0x2eff0000 },
 160     [VIRT_PCIE_PIO] =           { 0x3eff0000, 0x00010000 },
 161     [VIRT_PCIE_ECAM] =          { 0x3f000000, 0x01000000 },
 162     /* Actual RAM size depends on initial RAM and device memory settings */
 163     [VIRT_MEM] =                { GiB, LEGACY_RAMLIMIT_BYTES },
 164 };
 165
 166 /*
 167  * Highmem IO Regions: This memory map is floating, located after the RAM.
 168  * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
 169  * top of the RAM, so that its base get the same alignment as the size,
 170  * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
 171  * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
 172  * Note the extended_memmap is sized so that it eventually also includes the
 173  * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
 174  * index of base_memmap).
 175  */
 176 static MemMapEntry extended_memmap[] = {
 177     /* Additional 64 MB redist region (can contain up to 512 redistributors) */
 178     [VIRT_HIGH_GIC_REDIST2] =   { 0x0, 64 * MiB },
 179     [VIRT_HIGH_PCIE_ECAM] =     { 0x0, 256 * MiB },
 180     /* Second PCIe window */
 181     [VIRT_HIGH_PCIE_MMIO] =     { 0x0, 512 * GiB },
 182 };
 183
 184 static const int a15irqmap[] = {
 185     [VIRT_UART] = 1,
 186     [VIRT_RTC] = 2,
 187     [VIRT_PCIE] = 3, /* ... to 6 */
 188     [VIRT_GPIO] = 7,
 189     [VIRT_SECURE_UART] = 8,
 190     [VIRT_ACPI_GED] = 9,
 191     [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
 192     [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
 193     [VIRT_SMMU] = 74,    /* ...to 74 + NUM_SMMU_IRQS - 1 */
 194     [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
 195 };
 196
 197 static const char *valid_cpus[] = {
 198     ARM_CPU_TYPE_NAME("cortex-a7"),
 199     ARM_CPU_TYPE_NAME("cortex-a15"),
 200     ARM_CPU_TYPE_NAME("cortex-a53"),
 201     ARM_CPU_TYPE_NAME("cortex-a57"),
 202     ARM_CPU_TYPE_NAME("cortex-a72"),
 203     ARM_CPU_TYPE_NAME("host"),
 204     ARM_CPU_TYPE_NAME("max"),
 205 };
 206
 207 static bool cpu_type_valid(const char *cpu)
 208 {
 209     int i;
 210
 211     for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
 212         if (strcmp(cpu, valid_cpus[i]) == 0) {
 213             return true;
 214         }
 215     }
 216     return false;
 217 }
 218
 219 static void create_kaslr_seed(MachineState *ms, const char *node)
 220 {
 221     uint64_t seed;
 222
 223     if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
 224         return;
 225     }
 226     qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed);
 227 }
 228
 229 static void create_fdt(VirtMachineState *vms)
 230 {
 231     MachineState *ms = MACHINE(vms);
 232     int nb_numa_nodes = ms->numa_state->num_nodes;
 233     void *fdt = create_device_tree(&vms->fdt_size);
 234
 235     if (!fdt) {
 236         error_report("create_device_tree() failed");
 237         exit(1);
 238     }
 239
 240     ms->fdt = fdt;
 241
 242     /* Header */
 243     qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
 244     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 245     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 246
 247     /* /chosen must exist for load_dtb to fill in necessary properties later */
 248     qemu_fdt_add_subnode(fdt, "/chosen");
 249     create_kaslr_seed(ms, "/chosen");
 250
 251     if (vms->secure) {
 252         qemu_fdt_add_subnode(fdt, "/secure-chosen");
 253         create_kaslr_seed(ms, "/secure-chosen");
 254     }
 255
 256     /* Clock node, for the benefit of the UART. The kernel device tree
 257      * binding documentation claims the PL011 node clock properties are
 258      * optional but in practice if you omit them the kernel refuses to
 259      * probe for the device.
 260      */
 261     vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
 262     qemu_fdt_add_subnode(fdt, "/apb-pclk");
 263     qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
 264     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
 265     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
 266     qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
 267                                 "clk24mhz");
 268     qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
 269
 270     if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
 271         int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
 272         uint32_t *matrix = g_malloc0(size);
 273         int idx, i, j;
 274
 275         for (i = 0; i < nb_numa_nodes; i++) {
 276             for (j = 0; j < nb_numa_nodes; j++) {
 277                 idx = (i * nb_numa_nodes + j) * 3;
 278                 matrix[idx + 0] = cpu_to_be32(i);
 279                 matrix[idx + 1] = cpu_to_be32(j);
 280                 matrix[idx + 2] =
 281                     cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
 282             }
 283         }
 284
 285         qemu_fdt_add_subnode(fdt, "/distance-map");
 286         qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
 287                                 "numa-distance-map-v1");
 288         qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
 289                          matrix, size);
 290         g_free(matrix);
 291     }
 292 }
 293
 294 static void fdt_add_timer_nodes(const VirtMachineState *vms)
 295 {
 296     /* On real hardware these interrupts are level-triggered.
 297      * On KVM they were edge-triggered before host kernel version 4.4,
 298      * and level-triggered afterwards.
 299      * On emulated QEMU they are level-triggered.
 300      *
 301      * Getting the DTB info about them wrong is awkward for some
 302      * guest kernels:
 303      *  pre-4.8 ignore the DT and leave the interrupt configured
 304      *   with whatever the GIC reset value (or the bootloader) left it at
 305      *  4.8 before rc6 honour the incorrect data by programming it back
 306      *   into the GIC, causing problems
 307      *  4.8rc6 and later ignore the DT and always write "level triggered"
 308      *   into the GIC
 309      *
 310      * For backwards-compatibility, virt-2.8 and earlier will continue
 311      * to say these are edge-triggered, but later machines will report
 312      * the correct information.
 313      */
 314     ARMCPU *armcpu;
 315     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
 316     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
 317     MachineState *ms = MACHINE(vms);
 318
 319     if (vmc->claim_edge_triggered_timers) {
 320         irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
 321     }
 322
 323     if (vms->gic_version == VIRT_GIC_VERSION_2) {
 324         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
 325                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
 326                              (1 << MACHINE(vms)->smp.cpus) - 1);
 327     }
 328
 329     qemu_fdt_add_subnode(ms->fdt, "/timer");
 330
 331     armcpu = ARM_CPU(qemu_get_cpu(0));
 332     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
 333         const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
 334         qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
 335                          compat, sizeof(compat));
 336     } else {
 337         qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
 338                                 "arm,armv7-timer");
 339     }
 340     qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
 341     qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
 342                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
 343                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
 344                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
 345                        GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
 346 }
 347
 348 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
 349 {
 350     int cpu;
 351     int addr_cells = 1;
 352     const MachineState *ms = MACHINE(vms);
 353     int smp_cpus = ms->smp.cpus;
 354
 355     /*
 356      * From Documentation/devicetree/bindings/arm/cpus.txt
 357      *  On ARM v8 64-bit systems value should be set to 2,
 358      *  that corresponds to the MPIDR_EL1 register size.
 359      *  If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
 360      *  in the system, #address-cells can be set to 1, since
 361      *  MPIDR_EL1[63:32] bits are not used for CPUs
 362      *  identification.
 363      *
 364      *  Here we actually don't know whether our system is 32- or 64-bit one.
 365      *  The simplest way to go is to examine affinity IDs of all our CPUs. If
 366      *  at least one of them has Aff3 populated, we set #address-cells to 2.
 367      */
 368     for (cpu = 0; cpu < smp_cpus; cpu++) {
 369         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
 370
 371         if (armcpu->mp_affinity & ARM_AFF3_MASK) {
 372             addr_cells = 2;
 373             break;
 374         }
 375     }
 376
 377     qemu_fdt_add_subnode(ms->fdt, "/cpus");
 378     qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
 379     qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
 380
 381     for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
 382         char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 383         ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
 384         CPUState *cs = CPU(armcpu);
 385
 386         qemu_fdt_add_subnode(ms->fdt, nodename);
 387         qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
 388         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
 389                                     armcpu->dtb_compatible);
 390
 391         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
 392             qemu_fdt_setprop_string(ms->fdt, nodename,
 393                                         "enable-method", "psci");
 394         }
 395
 396         if (addr_cells == 2) {
 397             qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
 398                                  armcpu->mp_affinity);
 399         } else {
 400             qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
 401                                   armcpu->mp_affinity);
 402         }
 403
 404         if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
 405             qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
 406                 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
 407         }
 408
 409         g_free(nodename);
 410     }
 411 }
 412
 413 static void fdt_add_its_gic_node(VirtMachineState *vms)
 414 {
 415     char *nodename;
 416     MachineState *ms = MACHINE(vms);
 417
 418     vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
 419     nodename = g_strdup_printf("/intc/its@%" PRIx64,
 420                                vms->memmap[VIRT_GIC_ITS].base);
 421     qemu_fdt_add_subnode(ms->fdt, nodename);
 422     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
 423                             "arm,gic-v3-its");
 424     qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
 425     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 426                                  2, vms->memmap[VIRT_GIC_ITS].base,
 427                                  2, vms->memmap[VIRT_GIC_ITS].size);
 428     qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
 429     g_free(nodename);
 430 }
 431
 432 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
 433 {
 434     MachineState *ms = MACHINE(vms);
 435     char *nodename;
 436
 437     nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
 438                                vms->memmap[VIRT_GIC_V2M].base);
 439     vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
 440     qemu_fdt_add_subnode(ms->fdt, nodename);
 441     qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
 442                             "arm,gic-v2m-frame");
 443     qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
 444     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 445                                  2, vms->memmap[VIRT_GIC_V2M].base,
 446                                  2, vms->memmap[VIRT_GIC_V2M].size);
 447     qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
 448     g_free(nodename);
 449 }
 450
 451 static void fdt_add_gic_node(VirtMachineState *vms)
 452 {
 453     MachineState *ms = MACHINE(vms);
 454     char *nodename;
 455
 456     vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
 457     qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
 458
 459     nodename = g_strdup_printf("/intc@%" PRIx64,
 460                                vms->memmap[VIRT_GIC_DIST].base);
 461     qemu_fdt_add_subnode(ms->fdt, nodename);
 462     qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
 463     qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
 464     qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
 465     qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
 466     qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
 467     if (vms->gic_version == VIRT_GIC_VERSION_3) {
 468         int nb_redist_regions = virt_gicv3_redist_region_count(vms);
 469
 470         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
 471                                 "arm,gic-v3");
 472
 473         qemu_fdt_setprop_cell(ms->fdt, nodename,
 474                               "#redistributor-regions", nb_redist_regions);
 475
 476         if (nb_redist_regions == 1) {
 477             qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 478                                          2, vms->memmap[VIRT_GIC_DIST].base,
 479                                          2, vms->memmap[VIRT_GIC_DIST].size,
 480                                          2, vms->memmap[VIRT_GIC_REDIST].base,
 481                                          2, vms->memmap[VIRT_GIC_REDIST].size);
 482         } else {
 483             qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 484                                  2, vms->memmap[VIRT_GIC_DIST].base,
 485                                  2, vms->memmap[VIRT_GIC_DIST].size,
 486                                  2, vms->memmap[VIRT_GIC_REDIST].base,
 487                                  2, vms->memmap[VIRT_GIC_REDIST].size,
 488                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
 489                                  2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
 490         }
 491
 492         if (vms->virt) {
 493             qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
 494                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
 495                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 496         }
 497     } else {
 498         /* 'cortex-a15-gic' means 'GIC v2' */
 499         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
 500                                 "arm,cortex-a15-gic");
 501         if (!vms->virt) {
 502             qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 503                                          2, vms->memmap[VIRT_GIC_DIST].base,
 504                                          2, vms->memmap[VIRT_GIC_DIST].size,
 505                                          2, vms->memmap[VIRT_GIC_CPU].base,
 506                                          2, vms->memmap[VIRT_GIC_CPU].size);
 507         } else {
 508             qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 509                                          2, vms->memmap[VIRT_GIC_DIST].base,
 510                                          2, vms->memmap[VIRT_GIC_DIST].size,
 511                                          2, vms->memmap[VIRT_GIC_CPU].base,
 512                                          2, vms->memmap[VIRT_GIC_CPU].size,
 513                                          2, vms->memmap[VIRT_GIC_HYP].base,
 514                                          2, vms->memmap[VIRT_GIC_HYP].size,
 515                                          2, vms->memmap[VIRT_GIC_VCPU].base,
 516                                          2, vms->memmap[VIRT_GIC_VCPU].size);
 517             qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
 518                                    GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
 519                                    GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 520         }
 521     }
 522
 523     qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
 524     g_free(nodename);
 525 }
 526
 527 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
 528 {
 529     ARMCPU *armcpu = ARM_CPU(first_cpu);
 530     uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
 531     MachineState *ms = MACHINE(vms);
 532
 533     if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
 534         assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
 535         return;
 536     }
 537
 538     if (vms->gic_version == VIRT_GIC_VERSION_2) {
 539         irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
 540                              GIC_FDT_IRQ_PPI_CPU_WIDTH,
 541                              (1 << MACHINE(vms)->smp.cpus) - 1);
 542     }
 543
 544     qemu_fdt_add_subnode(ms->fdt, "/pmu");
 545     if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
 546         const char compat[] = "arm,armv8-pmuv3";
 547         qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
 548                          compat, sizeof(compat));
 549         qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
 550                                GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
 551     }
 552 }
 553
 554 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
 555 {
 556     DeviceState *dev;
 557     MachineState *ms = MACHINE(vms);
 558     int irq = vms->irqmap[VIRT_ACPI_GED];
 559     uint32_t event = ACPI_GED_PWR_DOWN_EVT;
 560
 561     if (ms->ram_slots) {
 562         event |= ACPI_GED_MEM_HOTPLUG_EVT;
 563     }
 564
 565     if (ms->nvdimms_state->is_enabled) {
 566         event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
 567     }
 568
 569     dev = qdev_new(TYPE_ACPI_GED);
 570     qdev_prop_set_uint32(dev, "ged-event", event);
 571
 572     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
 573     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
 574     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
 575
 576     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 577
 578     return dev;
 579 }
 580
 581 static void create_its(VirtMachineState *vms)
 582 {
 583     const char *itsclass = its_class_name();
 584     DeviceState *dev;
 585
 586     if (!itsclass) {
 587         /* Do nothing if not supported */
 588         return;
 589     }
 590
 591     dev = qdev_new(itsclass);
 592
 593     object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
 594                              &error_abort);
 595     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 596     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
 597
 598     fdt_add_its_gic_node(vms);
 599     vms->msi_controller = VIRT_MSI_CTRL_ITS;
 600 }
 601
 602 static void create_v2m(VirtMachineState *vms)
 603 {
 604     int i;
 605     int irq = vms->irqmap[VIRT_GIC_V2M];
 606     DeviceState *dev;
 607
 608     dev = qdev_new("arm-gicv2m");
 609     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
 610     qdev_prop_set_uint32(dev, "base-spi", irq);
 611     qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
 612     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 613
 614     for (i = 0; i < NUM_GICV2M_SPIS; i++) {
 615         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 616                            qdev_get_gpio_in(vms->gic, irq + i));
 617     }
 618
 619     fdt_add_v2m_gic_node(vms);
 620     vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
 621 }
 622
 623 static void create_gic(VirtMachineState *vms)
 624 {
 625     MachineState *ms = MACHINE(vms);
 626     /* We create a standalone GIC */
 627     SysBusDevice *gicbusdev;
 628     const char *gictype;
 629     int type = vms->gic_version, i;
 630     unsigned int smp_cpus = ms->smp.cpus;
 631     uint32_t nb_redist_regions = 0;
 632
 633     gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
 634
 635     vms->gic = qdev_new(gictype);
 636     qdev_prop_set_uint32(vms->gic, "revision", type);
 637     qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
 638     /* Note that the num-irq property counts both internal and external
 639      * interrupts; there are always 32 of the former (mandated by GIC spec).
 640      */
 641     qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
 642     if (!kvm_irqchip_in_kernel()) {
 643         qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
 644     }
 645
 646     if (type == 3) {
 647         uint32_t redist0_capacity =
 648                     vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
 649         uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
 650
 651         nb_redist_regions = virt_gicv3_redist_region_count(vms);
 652
 653         qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
 654                              nb_redist_regions);
 655         qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
 656
 657         if (nb_redist_regions == 2) {
 658             uint32_t redist1_capacity =
 659                     vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
 660
 661             qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
 662                 MIN(smp_cpus - redist0_count, redist1_capacity));
 663         }
 664     } else {
 665         if (!kvm_irqchip_in_kernel()) {
 666             qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
 667                               vms->virt);
 668         }
 669     }
 670     gicbusdev = SYS_BUS_DEVICE(vms->gic);
 671     sysbus_realize_and_unref(gicbusdev, &error_fatal);
 672     sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
 673     if (type == 3) {
 674         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
 675         if (nb_redist_regions == 2) {
 676             sysbus_mmio_map(gicbusdev, 2,
 677                             vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
 678         }
 679     } else {
 680         sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
 681         if (vms->virt) {
 682             sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
 683             sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
 684         }
 685     }
 686
 687     /* Wire the outputs from each CPU's generic timer and the GICv3
 688      * maintenance interrupt signal to the appropriate GIC PPI inputs,
 689      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
 690      */
 691     for (i = 0; i < smp_cpus; i++) {
 692         DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
 693         int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
 694         int irq;
 695         /* Mapping from the output timer irq lines from the CPU to the
 696          * GIC PPI inputs we use for the virt board.
 697          */
 698         const int timer_irq[] = {
 699             [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
 700             [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
 701             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
 702             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
 703         };
 704
 705         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 706             qdev_connect_gpio_out(cpudev, irq,
 707                                   qdev_get_gpio_in(vms->gic,
 708                                                    ppibase + timer_irq[irq]));
 709         }
 710
 711         if (type == 3) {
 712             qemu_irq irq = qdev_get_gpio_in(vms->gic,
 713                                             ppibase + ARCH_GIC_MAINT_IRQ);
 714             qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
 715                                         0, irq);
 716         } else if (vms->virt) {
 717             qemu_irq irq = qdev_get_gpio_in(vms->gic,
 718                                             ppibase + ARCH_GIC_MAINT_IRQ);
 719             sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
 720         }
 721
 722         qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
 723                                     qdev_get_gpio_in(vms->gic, ppibase
 724                                                      + VIRTUAL_PMU_IRQ));
 725
 726         sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
 727         sysbus_connect_irq(gicbusdev, i + smp_cpus,
 728                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
 729         sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
 730                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
 731         sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
 732                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
 733     }
 734
 735     fdt_add_gic_node(vms);
 736
 737     if (type == 3 && vms->its) {
 738         create_its(vms);
 739     } else if (type == 2) {
 740         create_v2m(vms);
 741     }
 742 }
 743
 744 static void create_uart(const VirtMachineState *vms, int uart,
 745                         MemoryRegion *mem, Chardev *chr)
 746 {
 747     char *nodename;
 748     hwaddr base = vms->memmap[uart].base;
 749     hwaddr size = vms->memmap[uart].size;
 750     int irq = vms->irqmap[uart];
 751     const char compat[] = "arm,pl011\0arm,primecell";
 752     const char clocknames[] = "uartclk\0apb_pclk";
 753     DeviceState *dev = qdev_new(TYPE_PL011);
 754     SysBusDevice *s = SYS_BUS_DEVICE(dev);
 755     MachineState *ms = MACHINE(vms);
 756
 757     qdev_prop_set_chr(dev, "chardev", chr);
 758     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 759     memory_region_add_subregion(mem, base,
 760                                 sysbus_mmio_get_region(s, 0));
 761     sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
 762
 763     nodename = g_strdup_printf("/pl011@%" PRIx64, base);
 764     qemu_fdt_add_subnode(ms->fdt, nodename);
 765     /* Note that we can't use setprop_string because of the embedded NUL */
 766     qemu_fdt_setprop(ms->fdt, nodename, "compatible",
 767                          compat, sizeof(compat));
 768     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 769                                      2, base, 2, size);
 770     qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
 771                                GIC_FDT_IRQ_TYPE_SPI, irq,
 772                                GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 773     qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
 774                                vms->clock_phandle, vms->clock_phandle);
 775     qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
 776                          clocknames, sizeof(clocknames));
 777
 778     if (uart == VIRT_UART) {
 779         qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
 780     } else {
 781         /* Mark as not usable by the normal world */
 782         qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
 783         qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
 784
 785         qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
 786                                 nodename);
 787     }
 788
 789     g_free(nodename);
 790 }
 791
 792 static void create_rtc(const VirtMachineState *vms)
 793 {
 794     char *nodename;
 795     hwaddr base = vms->memmap[VIRT_RTC].base;
 796     hwaddr size = vms->memmap[VIRT_RTC].size;
 797     int irq = vms->irqmap[VIRT_RTC];
 798     const char compat[] = "arm,pl031\0arm,primecell";
 799     MachineState *ms = MACHINE(vms);
 800
 801     sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
 802
 803     nodename = g_strdup_printf("/pl031@%" PRIx64, base);
 804     qemu_fdt_add_subnode(ms->fdt, nodename);
 805     qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
 806     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 807                                  2, base, 2, size);
 808     qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
 809                            GIC_FDT_IRQ_TYPE_SPI, irq,
 810                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 811     qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
 812     qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
 813     g_free(nodename);
 814 }
 815
 816 static DeviceState *gpio_key_dev;
 817 static void virt_powerdown_req(Notifier *n, void *opaque)
 818 {
 819     VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
 820
 821     if (s->acpi_dev) {
 822         acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
 823     } else {
 824         /* use gpio Pin 3 for power button event */
 825         qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
 826     }
 827 }
 828
 829 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
 830                              uint32_t phandle)
 831 {
 832     gpio_key_dev = sysbus_create_simple("gpio-key", -1,
 833                                         qdev_get_gpio_in(pl061_dev, 3));
 834
 835     qemu_fdt_add_subnode(fdt, "/gpio-keys");
 836     qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
 837     qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0);
 838     qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1);
 839
 840     qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
 841     qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
 842                             "label", "GPIO Key Poweroff");
 843     qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
 844                           KEY_POWER);
 845     qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
 846                            "gpios", phandle, 3, 0);
 847 }
 848
 849 #define SECURE_GPIO_POWEROFF 0
 850 #define SECURE_GPIO_RESET    1
 851
 852 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
 853                                    uint32_t phandle)
 854 {
 855     DeviceState *gpio_pwr_dev;
 856
 857     /* gpio-pwr */
 858     gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
 859
 860     /* connect secure pl061 to gpio-pwr */
 861     qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
 862                           qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
 863     qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
 864                           qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
 865
 866     qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
 867     qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
 868                             "gpio-poweroff");
 869     qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
 870                            "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
 871     qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
 872     qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
 873                             "okay");
 874
 875     qemu_fdt_add_subnode(fdt, "/gpio-restart");
 876     qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
 877                             "gpio-restart");
 878     qemu_fdt_setprop_cells(fdt, "/gpio-restart",
 879                            "gpios", phandle, SECURE_GPIO_RESET, 0);
 880     qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
 881     qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
 882                             "okay");
 883 }
 884
 885 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
 886                                 MemoryRegion *mem)
 887 {
 888     char *nodename;
 889     DeviceState *pl061_dev;
 890     hwaddr base = vms->memmap[gpio].base;
 891     hwaddr size = vms->memmap[gpio].size;
 892     int irq = vms->irqmap[gpio];
 893     const char compat[] = "arm,pl061\0arm,primecell";
 894     SysBusDevice *s;
 895     MachineState *ms = MACHINE(vms);
 896
 897     pl061_dev = qdev_new("pl061");
 898     s = SYS_BUS_DEVICE(pl061_dev);
 899     sysbus_realize_and_unref(s, &error_fatal);
 900     memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
 901     sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
 902
 903     uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
 904     nodename = g_strdup_printf("/pl061@%" PRIx64, base);
 905     qemu_fdt_add_subnode(ms->fdt, nodename);
 906     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 907                                  2, base, 2, size);
 908     qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
 909     qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
 910     qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
 911     qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
 912                            GIC_FDT_IRQ_TYPE_SPI, irq,
 913                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
 914     qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
 915     qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
 916     qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
 917
 918     if (gpio != VIRT_GPIO) {
 919         /* Mark as not usable by the normal world */
 920         qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
 921         qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
 922     }
 923     g_free(nodename);
 924
 925     /* Child gpio devices */
 926     if (gpio == VIRT_GPIO) {
 927         create_gpio_keys(ms->fdt, pl061_dev, phandle);
 928     } else {
 929         create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
 930     }
 931 }
 932
 933 static void create_virtio_devices(const VirtMachineState *vms)
 934 {
 935     int i;
 936     hwaddr size = vms->memmap[VIRT_MMIO].size;
 937     MachineState *ms = MACHINE(vms);
 938
 939     /* We create the transports in forwards order. Since qbus_realize()
 940      * prepends (not appends) new child buses, the incrementing loop below will
 941      * create a list of virtio-mmio buses with decreasing base addresses.
 942      *
 943      * When a -device option is processed from the command line,
 944      * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
 945      * order. The upshot is that -device options in increasing command line
 946      * order are mapped to virtio-mmio buses with decreasing base addresses.
 947      *
 948      * When this code was originally written, that arrangement ensured that the
 949      * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
 950      * the first -device on the command line. (The end-to-end order is a
 951      * function of this loop, qbus_realize(), qbus_find_recursive(), and the
 952      * guest kernel's name-to-address assignment strategy.)
 953      *
 954      * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
 955      * the message, if not necessarily the code, of commit 70161ff336.
 956      * Therefore the loop now establishes the inverse of the original intent.
 957      *
 958      * Unfortunately, we can't counteract the kernel change by reversing the
 959      * loop; it would break existing command lines.
 960      *
 961      * In any case, the kernel makes no guarantee about the stability of
 962      * enumeration order of virtio devices (as demonstrated by it changing
 963      * between kernel versions). For reliable and stable identification
 964      * of disks users must use UUIDs or similar mechanisms.
 965      */
 966     for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
 967         int irq = vms->irqmap[VIRT_MMIO] + i;
 968         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
 969
 970         sysbus_create_simple("virtio-mmio", base,
 971                              qdev_get_gpio_in(vms->gic, irq));
 972     }
 973
 974     /* We add dtb nodes in reverse order so that they appear in the finished
 975      * device tree lowest address first.
 976      *
 977      * Note that this mapping is independent of the loop above. The previous
 978      * loop influences virtio device to virtio transport assignment, whereas
 979      * this loop controls how virtio transports are laid out in the dtb.
 980      */
 981     for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
 982         char *nodename;
 983         int irq = vms->irqmap[VIRT_MMIO] + i;
 984         hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
 985
 986         nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
 987         qemu_fdt_add_subnode(ms->fdt, nodename);
 988         qemu_fdt_setprop_string(ms->fdt, nodename,
 989                                 "compatible", "virtio,mmio");
 990         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
 991                                      2, base, 2, size);
 992         qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
 993                                GIC_FDT_IRQ_TYPE_SPI, irq,
 994                                GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
 995         qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
 996         g_free(nodename);
 997     }
 998 }
 999
1000 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1001
1002 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1003                                         const char *name,
1004                                         const char *alias_prop_name)
1005 {
1006     /*
1007      * Create a single flash device.  We use the same parameters as
1008      * the flash devices on the Versatile Express board.
1009      */
1010     DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1011
1012     qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1013     qdev_prop_set_uint8(dev, "width", 4);
1014     qdev_prop_set_uint8(dev, "device-width", 2);
1015     qdev_prop_set_bit(dev, "big-endian", false);
1016     qdev_prop_set_uint16(dev, "id0", 0x89);
1017     qdev_prop_set_uint16(dev, "id1", 0x18);
1018     qdev_prop_set_uint16(dev, "id2", 0x00);
1019     qdev_prop_set_uint16(dev, "id3", 0x00);
1020     qdev_prop_set_string(dev, "name", name);
1021     object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1022     object_property_add_alias(OBJECT(vms), alias_prop_name,
1023                               OBJECT(dev), "drive");
1024     return PFLASH_CFI01(dev);
1025 }
1026
1027 static void virt_flash_create(VirtMachineState *vms)
1028 {
1029     vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1030     vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1031 }
1032
1033 static void virt_flash_map1(PFlashCFI01 *flash,
1034                             hwaddr base, hwaddr size,
1035                             MemoryRegion *sysmem)
1036 {
1037     DeviceState *dev = DEVICE(flash);
1038
1039     assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1040     assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1041     qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1042     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1043
1044     memory_region_add_subregion(sysmem, base,
1045                                 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1046                                                        0));
1047 }
1048
1049 static void virt_flash_map(VirtMachineState *vms,
1050                            MemoryRegion *sysmem,
1051                            MemoryRegion *secure_sysmem)
1052 {
1053     /*
1054      * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1055      * sysmem is the system memory space. secure_sysmem is the secure view
1056      * of the system, and the first flash device should be made visible only
1057      * there. The second flash device is visible to both secure and nonsecure.
1058      * If sysmem == secure_sysmem this means there is no separate Secure
1059      * address space and both flash devices are generally visible.
1060      */
1061     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1062     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1063
1064     virt_flash_map1(vms->flash[0], flashbase, flashsize,
1065                     secure_sysmem);
1066     virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1067                     sysmem);
1068 }
1069
1070 static void virt_flash_fdt(VirtMachineState *vms,
1071                            MemoryRegion *sysmem,
1072                            MemoryRegion *secure_sysmem)
1073 {
1074     hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1075     hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1076     MachineState *ms = MACHINE(vms);
1077     char *nodename;
1078
1079     if (sysmem == secure_sysmem) {
1080         /* Report both flash devices as a single node in the DT */
1081         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1082         qemu_fdt_add_subnode(ms->fdt, nodename);
1083         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1084         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1085                                      2, flashbase, 2, flashsize,
1086                                      2, flashbase + flashsize, 2, flashsize);
1087         qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1088         g_free(nodename);
1089     } else {
1090         /*
1091          * Report the devices as separate nodes so we can mark one as
1092          * only visible to the secure world.
1093          */
1094         nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1095         qemu_fdt_add_subnode(ms->fdt, nodename);
1096         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1097         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1098                                      2, flashbase, 2, flashsize);
1099         qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1100         qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1101         qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1102         g_free(nodename);
1103
1104         nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1105         qemu_fdt_add_subnode(ms->fdt, nodename);
1106         qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1107         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1108                                      2, flashbase + flashsize, 2, flashsize);
1109         qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1110         g_free(nodename);
1111     }
1112 }
1113
1114 static bool virt_firmware_init(VirtMachineState *vms,
1115                                MemoryRegion *sysmem,
1116                                MemoryRegion *secure_sysmem)
1117 {
1118     int i;
1119     const char *bios_name;
1120     BlockBackend *pflash_blk0;
1121
1122     /* Map legacy -drive if=pflash to machine properties */
1123     for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1124         pflash_cfi01_legacy_drive(vms->flash[i],
1125                                   drive_get(IF_PFLASH, 0, i));
1126     }
1127
1128     virt_flash_map(vms, sysmem, secure_sysmem);
1129
1130     pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1131
1132     bios_name = MACHINE(vms)->firmware;
1133     if (bios_name) {
1134         char *fname;
1135         MemoryRegion *mr;
1136         int image_size;
1137
1138         if (pflash_blk0) {
1139             error_report("The contents of the first flash device may be "
1140                          "specified with -bios or with -drive if=pflash... "
1141                          "but you cannot use both options at once");
1142             exit(1);
1143         }
1144
1145         /* Fall back to -bios */
1146
1147         fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1148         if (!fname) {
1149             error_report("Could not find ROM image '%s'", bios_name);
1150             exit(1);
1151         }
1152         mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1153         image_size = load_image_mr(fname, mr);
1154         g_free(fname);
1155         if (image_size < 0) {
1156             error_report("Could not load ROM image '%s'", bios_name);
1157             exit(1);
1158         }
1159     }
1160
1161     return pflash_blk0 || bios_name;
1162 }
1163
1164 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1165 {
1166     MachineState *ms = MACHINE(vms);
1167     hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1168     hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1169     FWCfgState *fw_cfg;
1170     char *nodename;
1171
1172     fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1173     fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1174
1175     nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1176     qemu_fdt_add_subnode(ms->fdt, nodename);
1177     qemu_fdt_setprop_string(ms->fdt, nodename,
1178                             "compatible", "qemu,fw-cfg-mmio");
1179     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1180                                  2, base, 2, size);
1181     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1182     g_free(nodename);
1183     return fw_cfg;
1184 }
1185
1186 static void create_pcie_irq_map(const MachineState *ms,
1187                                 uint32_t gic_phandle,
1188                                 int first_irq, const char *nodename)
1189 {
1190     int devfn, pin;
1191     uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1192     uint32_t *irq_map = full_irq_map;
1193
1194     for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1195         for (pin = 0; pin < 4; pin++) {
1196             int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1197             int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1198             int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1199             int i;
1200
1201             uint32_t map[] = {
1202                 devfn << 8, 0, 0,                           /* devfn */
1203                 pin + 1,                                    /* PCI pin */
1204                 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1205
1206             /* Convert map to big endian */
1207             for (i = 0; i < 10; i++) {
1208                 irq_map[i] = cpu_to_be32(map[i]);
1209             }
1210             irq_map += 10;
1211         }
1212     }
1213
1214     qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1215                      full_irq_map, sizeof(full_irq_map));
1216
1217     qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1218                            cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1219                            0, 0,
1220                            0x7           /* PCI irq */);
1221 }
1222
1223 static void create_smmu(const VirtMachineState *vms,
1224                         PCIBus *bus)
1225 {
1226     char *node;
1227     const char compat[] = "arm,smmu-v3";
1228     int irq =  vms->irqmap[VIRT_SMMU];
1229     int i;
1230     hwaddr base = vms->memmap[VIRT_SMMU].base;
1231     hwaddr size = vms->memmap[VIRT_SMMU].size;
1232     const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1233     DeviceState *dev;
1234     MachineState *ms = MACHINE(vms);
1235
1236     if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1237         return;
1238     }
1239
1240     dev = qdev_new("arm-smmuv3");
1241
1242     object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1243                              &error_abort);
1244     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1245     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1246     for (i = 0; i < NUM_SMMU_IRQS; i++) {
1247         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1248                            qdev_get_gpio_in(vms->gic, irq + i));
1249     }
1250
1251     node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1252     qemu_fdt_add_subnode(ms->fdt, node);
1253     qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1254     qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1255
1256     qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1257             GIC_FDT_IRQ_TYPE_SPI, irq    , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1258             GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1259             GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1260             GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1261
1262     qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1263                      sizeof(irq_names));
1264
1265     qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
1266     qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
1267     qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1268
1269     qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1270
1271     qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1272     g_free(node);
1273 }
1274
1275 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1276 {
1277     const char compat[] = "virtio,pci-iommu";
1278     uint16_t bdf = vms->virtio_iommu_bdf;
1279     MachineState *ms = MACHINE(vms);
1280     char *node;
1281
1282     vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1283
1284     node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf);
1285     qemu_fdt_add_subnode(ms->fdt, node);
1286     qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1287     qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1288                                  1, bdf << 8, 1, 0, 1, 0,
1289                                  1, 0, 1, 0);
1290
1291     qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1292     qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1293     g_free(node);
1294
1295     qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1296                            0x0, vms->iommu_phandle, 0x0, bdf,
1297                            bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1298 }
1299
1300 static void create_pcie(VirtMachineState *vms)
1301 {
1302     hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1303     hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1304     hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1305     hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1306     hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1307     hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1308     hwaddr base_ecam, size_ecam;
1309     hwaddr base = base_mmio;
1310     int nr_pcie_buses;
1311     int irq = vms->irqmap[VIRT_PCIE];
1312     MemoryRegion *mmio_alias;
1313     MemoryRegion *mmio_reg;
1314     MemoryRegion *ecam_alias;
1315     MemoryRegion *ecam_reg;
1316     DeviceState *dev;
1317     char *nodename;
1318     int i, ecam_id;
1319     PCIHostState *pci;
1320     MachineState *ms = MACHINE(vms);
1321
1322     dev = qdev_new(TYPE_GPEX_HOST);
1323     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1324
1325     ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1326     base_ecam = vms->memmap[ecam_id].base;
1327     size_ecam = vms->memmap[ecam_id].size;
1328     nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1329     /* Map only the first size_ecam bytes of ECAM space */
1330     ecam_alias = g_new0(MemoryRegion, 1);
1331     ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1332     memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1333                              ecam_reg, 0, size_ecam);
1334     memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1335
1336     /* Map the MMIO window into system address space so as to expose
1337      * the section of PCI MMIO space which starts at the same base address
1338      * (ie 1:1 mapping for that part of PCI MMIO space visible through
1339      * the window).
1340      */
1341     mmio_alias = g_new0(MemoryRegion, 1);
1342     mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1343     memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1344                              mmio_reg, base_mmio, size_mmio);
1345     memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1346
1347     if (vms->highmem) {
1348         /* Map high MMIO space */
1349         MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1350
1351         memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1352                                  mmio_reg, base_mmio_high, size_mmio_high);
1353         memory_region_add_subregion(get_system_memory(), base_mmio_high,
1354                                     high_mmio_alias);
1355     }
1356
1357     /* Map IO port space */
1358     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1359
1360     for (i = 0; i < GPEX_NUM_IRQS; i++) {
1361         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1362                            qdev_get_gpio_in(vms->gic, irq + i));
1363         gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1364     }
1365
1366     pci = PCI_HOST_BRIDGE(dev);
1367     vms->bus = pci->bus;
1368     if (vms->bus) {
1369         for (i = 0; i < nb_nics; i++) {
1370             NICInfo *nd = &nd_table[i];
1371
1372             if (!nd->model) {
1373                 nd->model = g_strdup("virtio");
1374             }
1375
1376             pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1377         }
1378     }
1379
1380     nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1381     qemu_fdt_add_subnode(ms->fdt, nodename);
1382     qemu_fdt_setprop_string(ms->fdt, nodename,
1383                             "compatible", "pci-host-ecam-generic");
1384     qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1385     qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1386     qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1387     qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1388     qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1389                            nr_pcie_buses - 1);
1390     qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1391
1392     if (vms->msi_phandle) {
1393         qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
1394                                vms->msi_phandle);
1395     }
1396
1397     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1398                                  2, base_ecam, 2, size_ecam);
1399
1400     if (vms->highmem) {
1401         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1402                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1403                                      2, base_pio, 2, size_pio,
1404                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1405                                      2, base_mmio, 2, size_mmio,
1406                                      1, FDT_PCI_RANGE_MMIO_64BIT,
1407                                      2, base_mmio_high,
1408                                      2, base_mmio_high, 2, size_mmio_high);
1409     } else {
1410         qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1411                                      1, FDT_PCI_RANGE_IOPORT, 2, 0,
1412                                      2, base_pio, 2, size_pio,
1413                                      1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1414                                      2, base_mmio, 2, size_mmio);
1415     }
1416
1417     qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1418     create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1419
1420     if (vms->iommu) {
1421         vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1422
1423         switch (vms->iommu) {
1424         case VIRT_IOMMU_SMMUV3:
1425             create_smmu(vms, vms->bus);
1426             qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1427                                    0x0, vms->iommu_phandle, 0x0, 0x10000);
1428             break;
1429         default:
1430             g_assert_not_reached();
1431         }
1432     }
1433 }
1434
1435 static void create_platform_bus(VirtMachineState *vms)
1436 {
1437     DeviceState *dev;
1438     SysBusDevice *s;
1439     int i;
1440     MemoryRegion *sysmem = get_system_memory();
1441
1442     dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1443     dev->id = TYPE_PLATFORM_BUS_DEVICE;
1444     qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1445     qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1446     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1447     vms->platform_bus_dev = dev;
1448
1449     s = SYS_BUS_DEVICE(dev);
1450     for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1451         int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1452         sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1453     }
1454
1455     memory_region_add_subregion(sysmem,
1456                                 vms->memmap[VIRT_PLATFORM_BUS].base,
1457                                 sysbus_mmio_get_region(s, 0));
1458 }
1459
1460 static void create_tag_ram(MemoryRegion *tag_sysmem,
1461                            hwaddr base, hwaddr size,
1462                            const char *name)
1463 {
1464     MemoryRegion *tagram = g_new(MemoryRegion, 1);
1465
1466     memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1467     memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1468 }
1469
1470 static void create_secure_ram(VirtMachineState *vms,
1471                               MemoryRegion *secure_sysmem,
1472                               MemoryRegion *secure_tag_sysmem)
1473 {
1474     MemoryRegion *secram = g_new(MemoryRegion, 1);
1475     char *nodename;
1476     hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1477     hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1478     MachineState *ms = MACHINE(vms);
1479
1480     memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1481                            &error_fatal);
1482     memory_region_add_subregion(secure_sysmem, base, secram);
1483
1484     nodename = g_strdup_printf("/secram@%" PRIx64, base);
1485     qemu_fdt_add_subnode(ms->fdt, nodename);
1486     qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1487     qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1488     qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1489     qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1490
1491     if (secure_tag_sysmem) {
1492         create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1493     }
1494
1495     g_free(nodename);
1496 }
1497
1498 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1499 {
1500     const VirtMachineState *board = container_of(binfo, VirtMachineState,
1501                                                  bootinfo);
1502     MachineState *ms = MACHINE(board);
1503
1504
1505     *fdt_size = board->fdt_size;
1506     return ms->fdt;
1507 }
1508
1509 static void virt_build_smbios(VirtMachineState *vms)
1510 {
1511     MachineClass *mc = MACHINE_GET_CLASS(vms);
1512     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1513     uint8_t *smbios_tables, *smbios_anchor;
1514     size_t smbios_tables_len, smbios_anchor_len;
1515     const char *product = "QEMU Virtual Machine";
1516
1517     if (kvm_enabled()) {
1518         product = "KVM Virtual Machine";
1519     }
1520
1521     smbios_set_defaults("QEMU", product,
1522                         vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1523                         true, SMBIOS_ENTRY_POINT_30);
1524
1525     smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len,
1526                       &smbios_anchor, &smbios_anchor_len);
1527
1528     if (smbios_anchor) {
1529         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1530                         smbios_tables, smbios_tables_len);
1531         fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1532                         smbios_anchor, smbios_anchor_len);
1533     }
1534 }
1535
1536 static
1537 void virt_machine_done(Notifier *notifier, void *data)
1538 {
1539     VirtMachineState *vms = container_of(notifier, VirtMachineState,
1540                                          machine_done);
1541     MachineState *ms = MACHINE(vms);
1542     ARMCPU *cpu = ARM_CPU(first_cpu);
1543     struct arm_boot_info *info = &vms->bootinfo;
1544     AddressSpace *as = arm_boot_address_space(cpu, info);
1545
1546     /*
1547      * If the user provided a dtb, we assume the dynamic sysbus nodes
1548      * already are integrated there. This corresponds to a use case where
1549      * the dynamic sysbus nodes are complex and their generation is not yet
1550      * supported. In that case the user can take charge of the guest dt
1551      * while qemu takes charge of the qom stuff.
1552      */
1553     if (info->dtb_filename == NULL) {
1554         platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1555                                        vms->memmap[VIRT_PLATFORM_BUS].base,
1556                                        vms->memmap[VIRT_PLATFORM_BUS].size,
1557                                        vms->irqmap[VIRT_PLATFORM_BUS]);
1558     }
1559     if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1560         exit(1);
1561     }
1562
1563     fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1564
1565     virt_acpi_setup(vms);
1566     virt_build_smbios(vms);
1567 }
1568
1569 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1570 {
1571     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1572     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1573
1574     if (!vmc->disallow_affinity_adjustment) {
1575         /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1576          * GIC's target-list limitations. 32-bit KVM hosts currently
1577          * always create clusters of 4 CPUs, but that is expected to
1578          * change when they gain support for gicv3. When KVM is enabled
1579          * it will override the changes we make here, therefore our
1580          * purposes are to make TCG consistent (with 64-bit KVM hosts)
1581          * and to improve SGI efficiency.
1582          */
1583         if (vms->gic_version == VIRT_GIC_VERSION_3) {
1584             clustersz = GICV3_TARGETLIST_BITS;
1585         } else {
1586             clustersz = GIC_TARGETLIST_BITS;
1587         }
1588     }
1589     return arm_cpu_mp_affinity(idx, clustersz);
1590 }
1591
1592 static void virt_set_memmap(VirtMachineState *vms)
1593 {
1594     MachineState *ms = MACHINE(vms);
1595     hwaddr base, device_memory_base, device_memory_size;
1596     int i;
1597
1598     vms->memmap = extended_memmap;
1599
1600     for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1601         vms->memmap[i] = base_memmap[i];
1602     }
1603
1604     if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1605         error_report("unsupported number of memory slots: %"PRIu64,
1606                      ms->ram_slots);
1607         exit(EXIT_FAILURE);
1608     }
1609
1610     /*
1611      * We compute the base of the high IO region depending on the
1612      * amount of initial and device memory. The device memory start/size
1613      * is aligned on 1GiB. We never put the high IO region below 256GiB
1614      * so that if maxram_size is < 255GiB we keep the legacy memory map.
1615      * The device region size assumes 1GiB page max alignment per slot.
1616      */
1617     device_memory_base =
1618         ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1619     device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1620
1621     /* Base address of the high IO region */
1622     base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1623     if (base < device_memory_base) {
1624         error_report("maxmem/slots too huge");
1625         exit(EXIT_FAILURE);
1626     }
1627     if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1628         base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1629     }
1630
1631     for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1632         hwaddr size = extended_memmap[i].size;
1633
1634         base = ROUND_UP(base, size);
1635         vms->memmap[i].base = base;
1636         vms->memmap[i].size = size;
1637         base += size;
1638     }
1639     vms->highest_gpa = base - 1;
1640     if (device_memory_size > 0) {
1641         ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1642         ms->device_memory->base = device_memory_base;
1643         memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1644                            "device-memory", device_memory_size);
1645     }
1646 }
1647
1648 /*
1649  * finalize_gic_version - Determines the final gic_version
1650  * according to the gic-version property
1651  *
1652  * Default GIC type is v2
1653  */
1654 static void finalize_gic_version(VirtMachineState *vms)
1655 {
1656     unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1657
1658     if (kvm_enabled()) {
1659         int probe_bitmap;
1660
1661         if (!kvm_irqchip_in_kernel()) {
1662             switch (vms->gic_version) {
1663             case VIRT_GIC_VERSION_HOST:
1664                 warn_report(
1665                     "gic-version=host not relevant with kernel-irqchip=off "
1666                      "as only userspace GICv2 is supported. Using v2 ...");
1667                 return;
1668             case VIRT_GIC_VERSION_MAX:
1669             case VIRT_GIC_VERSION_NOSEL:
1670                 vms->gic_version = VIRT_GIC_VERSION_2;
1671                 return;
1672             case VIRT_GIC_VERSION_2:
1673                 return;
1674             case VIRT_GIC_VERSION_3:
1675                 error_report(
1676                     "gic-version=3 is not supported with kernel-irqchip=off");
1677                 exit(1);
1678             }
1679         }
1680
1681         probe_bitmap = kvm_arm_vgic_probe();
1682         if (!probe_bitmap) {
1683             error_report("Unable to determine GIC version supported by host");
1684             exit(1);
1685         }
1686
1687         switch (vms->gic_version) {
1688         case VIRT_GIC_VERSION_HOST:
1689         case VIRT_GIC_VERSION_MAX:
1690             if (probe_bitmap & KVM_ARM_VGIC_V3) {
1691                 vms->gic_version = VIRT_GIC_VERSION_3;
1692             } else {
1693                 vms->gic_version = VIRT_GIC_VERSION_2;
1694             }
1695             return;
1696         case VIRT_GIC_VERSION_NOSEL:
1697             if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
1698                 vms->gic_version = VIRT_GIC_VERSION_2;
1699             } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
1700                 /*
1701                  * in case the host does not support v2 in-kernel emulation or
1702                  * the end-user requested more than 8 VCPUs we now default
1703                  * to v3. In any case defaulting to v2 would be broken.
1704                  */
1705                 vms->gic_version = VIRT_GIC_VERSION_3;
1706             } else if (max_cpus > GIC_NCPU) {
1707                 error_report("host only supports in-kernel GICv2 emulation "
1708                              "but more than 8 vcpus are requested");
1709                 exit(1);
1710             }
1711             break;
1712         case VIRT_GIC_VERSION_2:
1713         case VIRT_GIC_VERSION_3:
1714             break;
1715         }
1716
1717         /* Check chosen version is effectively supported by the host */
1718         if (vms->gic_version == VIRT_GIC_VERSION_2 &&
1719             !(probe_bitmap & KVM_ARM_VGIC_V2)) {
1720             error_report("host does not support in-kernel GICv2 emulation");
1721             exit(1);
1722         } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
1723                    !(probe_bitmap & KVM_ARM_VGIC_V3)) {
1724             error_report("host does not support in-kernel GICv3 emulation");
1725             exit(1);
1726         }
1727         return;
1728     }
1729
1730     /* TCG mode */
1731     switch (vms->gic_version) {
1732     case VIRT_GIC_VERSION_NOSEL:
1733         vms->gic_version = VIRT_GIC_VERSION_2;
1734         break;
1735     case VIRT_GIC_VERSION_MAX:
1736         vms->gic_version = VIRT_GIC_VERSION_3;
1737         break;
1738     case VIRT_GIC_VERSION_HOST:
1739         error_report("gic-version=host requires KVM");
1740         exit(1);
1741     case VIRT_GIC_VERSION_2:
1742     case VIRT_GIC_VERSION_3:
1743         break;
1744     }
1745 }
1746
1747 /*
1748  * virt_cpu_post_init() must be called after the CPUs have
1749  * been realized and the GIC has been created.
1750  */
1751 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
1752 {
1753     int max_cpus = MACHINE(vms)->smp.max_cpus;
1754     bool aarch64, pmu, steal_time;
1755     CPUState *cpu;
1756
1757     aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
1758     pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
1759     steal_time = object_property_get_bool(OBJECT(first_cpu),
1760                                           "kvm-steal-time", NULL);
1761
1762     if (kvm_enabled()) {
1763         hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1764         hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1765
1766         if (steal_time) {
1767             MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1768             hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1769
1770             /* The memory region size must be a multiple of host page size. */
1771             pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1772
1773             if (pvtime_size > pvtime_reg_size) {
1774                 error_report("pvtime requires a %" HWADDR_PRId
1775                              " byte memory region for %d CPUs,"
1776                              " but only %" HWADDR_PRId " has been reserved",
1777                              pvtime_size, max_cpus, pvtime_reg_size);
1778                 exit(1);
1779             }
1780
1781             memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1782             memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1783         }
1784
1785         CPU_FOREACH(cpu) {
1786             if (pmu) {
1787                 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1788                 if (kvm_irqchip_in_kernel()) {
1789                     kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
1790                 }
1791                 kvm_arm_pmu_init(cpu);
1792             }
1793             if (steal_time) {
1794                 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
1795                                          cpu->cpu_index * PVTIME_SIZE_PER_CPU);
1796             }
1797         }
1798     } else {
1799         if (aarch64 && vms->highmem) {
1800             int requested_pa_size = 64 - clz64(vms->highest_gpa);
1801             int pamax = arm_pamax(ARM_CPU(first_cpu));
1802
1803             if (pamax < requested_pa_size) {
1804                 error_report("VCPU supports less PA bits (%d) than "
1805                              "requested by the memory map (%d)",
1806                              pamax, requested_pa_size);
1807                 exit(1);
1808             }
1809         }
1810     }
1811 }
1812
1813 static void machvirt_init(MachineState *machine)
1814 {
1815     VirtMachineState *vms = VIRT_MACHINE(machine);
1816     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1817     MachineClass *mc = MACHINE_GET_CLASS(machine);
1818     const CPUArchIdList *possible_cpus;
1819     MemoryRegion *sysmem = get_system_memory();
1820     MemoryRegion *secure_sysmem = NULL;
1821     MemoryRegion *tag_sysmem = NULL;
1822     MemoryRegion *secure_tag_sysmem = NULL;
1823     int n, virt_max_cpus;
1824     bool firmware_loaded;
1825     bool aarch64 = true;
1826     bool has_ged = !vmc->no_ged;
1827     unsigned int smp_cpus = machine->smp.cpus;
1828     unsigned int max_cpus = machine->smp.max_cpus;
1829
1830     /*
1831      * In accelerated mode, the memory map is computed earlier in kvm_type()
1832      * to create a VM with the right number of IPA bits.
1833      */
1834     if (!vms->memmap) {
1835         virt_set_memmap(vms);
1836     }
1837
1838     /* We can probe only here because during property set
1839      * KVM is not available yet
1840      */
1841     finalize_gic_version(vms);
1842
1843     if (!cpu_type_valid(machine->cpu_type)) {
1844         error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1845         exit(1);
1846     }
1847
1848     if (vms->secure) {
1849         if (kvm_enabled()) {
1850             error_report("mach-virt: KVM does not support Security extensions");
1851             exit(1);
1852         }
1853
1854         /*
1855          * The Secure view of the world is the same as the NonSecure,
1856          * but with a few extra devices. Create it as a container region
1857          * containing the system memory at low priority; any secure-only
1858          * devices go in at higher priority and take precedence.
1859          */
1860         secure_sysmem = g_new(MemoryRegion, 1);
1861         memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1862                            UINT64_MAX);
1863         memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1864     }
1865
1866     firmware_loaded = virt_firmware_init(vms, sysmem,
1867                                          secure_sysmem ?: sysmem);
1868
1869     /* If we have an EL3 boot ROM then the assumption is that it will
1870      * implement PSCI itself, so disable QEMU's internal implementation
1871      * so it doesn't get in the way. Instead of starting secondary
1872      * CPUs in PSCI powerdown state we will start them all running and
1873      * let the boot ROM sort them out.
1874      * The usual case is that we do use QEMU's PSCI implementation;
1875      * if the guest has EL2 then we will use SMC as the conduit,
1876      * and otherwise we will use HVC (for backwards compatibility and
1877      * because if we're using KVM then we must use HVC).
1878      */
1879     if (vms->secure && firmware_loaded) {
1880         vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1881     } else if (vms->virt) {
1882         vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1883     } else {
1884         vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1885     }
1886
1887     /* The maximum number of CPUs depends on the GIC version, or on how
1888      * many redistributors we can fit into the memory map.
1889      */
1890     if (vms->gic_version == VIRT_GIC_VERSION_3) {
1891         virt_max_cpus =
1892             vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1893         virt_max_cpus +=
1894             vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1895     } else {
1896         virt_max_cpus = GIC_NCPU;
1897     }
1898
1899     if (max_cpus > virt_max_cpus) {
1900         error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1901                      "supported by machine 'mach-virt' (%d)",
1902                      max_cpus, virt_max_cpus);
1903         exit(1);
1904     }
1905
1906     if (vms->virt && kvm_enabled()) {
1907         error_report("mach-virt: KVM does not support providing "
1908                      "Virtualization extensions to the guest CPU");
1909         exit(1);
1910     }
1911
1912     if (vms->mte && kvm_enabled()) {
1913         error_report("mach-virt: KVM does not support providing "
1914                      "MTE to the guest CPU");
1915         exit(1);
1916     }
1917
1918     create_fdt(vms);
1919
1920     possible_cpus = mc->possible_cpu_arch_ids(machine);
1921     assert(possible_cpus->len == max_cpus);
1922     for (n = 0; n < possible_cpus->len; n++) {
1923         Object *cpuobj;
1924         CPUState *cs;
1925
1926         if (n >= smp_cpus) {
1927             break;
1928         }
1929
1930         cpuobj = object_new(possible_cpus->cpus[n].type);
1931         object_property_set_int(cpuobj, "mp-affinity",
1932                                 possible_cpus->cpus[n].arch_id, NULL);
1933
1934         cs = CPU(cpuobj);
1935         cs->cpu_index = n;
1936
1937         numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1938                           &error_fatal);
1939
1940         aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1941
1942         if (!vms->secure) {
1943             object_property_set_bool(cpuobj, "has_el3", false, NULL);
1944         }
1945
1946         if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
1947             object_property_set_bool(cpuobj, "has_el2", false, NULL);
1948         }
1949
1950         if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1951             object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit,
1952                                     NULL);
1953
1954             /* Secondary CPUs start in PSCI powered-down state */
1955             if (n > 0) {
1956                 object_property_set_bool(cpuobj, "start-powered-off", true,
1957                                          NULL);
1958             }
1959         }
1960
1961         if (vmc->kvm_no_adjvtime &&
1962             object_property_find(cpuobj, "kvm-no-adjvtime")) {
1963             object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
1964         }
1965
1966         if (vmc->no_kvm_steal_time &&
1967             object_property_find(cpuobj, "kvm-steal-time")) {
1968             object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
1969         }
1970
1971         if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
1972             object_property_set_bool(cpuobj, "pmu", false, NULL);
1973         }
1974
1975         if (object_property_find(cpuobj, "reset-cbar")) {
1976             object_property_set_int(cpuobj, "reset-cbar",
1977                                     vms->memmap[VIRT_CPUPERIPHS].base,
1978                                     &error_abort);
1979         }
1980
1981         object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
1982                                  &error_abort);
1983         if (vms->secure) {
1984             object_property_set_link(cpuobj, "secure-memory",
1985                                      OBJECT(secure_sysmem), &error_abort);
1986         }
1987
1988         if (vms->mte) {
1989             /* Create the memory region only once, but link to all cpus. */
1990             if (!tag_sysmem) {
1991                 /*
1992                  * The property exists only if MemTag is supported.
1993                  * If it is, we must allocate the ram to back that up.
1994                  */
1995                 if (!object_property_find(cpuobj, "tag-memory")) {
1996                     error_report("MTE requested, but not supported "
1997                                  "by the guest CPU");
1998                     exit(1);
1999                 }
2000
2001                 tag_sysmem = g_new(MemoryRegion, 1);
2002                 memory_region_init(tag_sysmem, OBJECT(machine),
2003                                    "tag-memory", UINT64_MAX / 32);
2004
2005                 if (vms->secure) {
2006                     secure_tag_sysmem = g_new(MemoryRegion, 1);
2007                     memory_region_init(secure_tag_sysmem, OBJECT(machine),
2008                                        "secure-tag-memory", UINT64_MAX / 32);
2009
2010                     /* As with ram, secure-tag takes precedence over tag.  */
2011                     memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2012                                                         tag_sysmem, -1);
2013                 }
2014             }
2015
2016             object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2017                                      &error_abort);
2018             if (vms->secure) {
2019                 object_property_set_link(cpuobj, "secure-tag-memory",
2020                                          OBJECT(secure_tag_sysmem),
2021                                          &error_abort);
2022             }
2023         }
2024
2025         qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2026         object_unref(cpuobj);
2027     }
2028     fdt_add_timer_nodes(vms);
2029     fdt_add_cpu_nodes(vms);
2030
2031     memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2032                                 machine->ram);
2033     if (machine->device_memory) {
2034         memory_region_add_subregion(sysmem, machine->device_memory->base,
2035                                     &machine->device_memory->mr);
2036     }
2037
2038     virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2039
2040     create_gic(vms);
2041
2042     virt_cpu_post_init(vms, sysmem);
2043
2044     fdt_add_pmu_nodes(vms);
2045
2046     create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
2047
2048     if (vms->secure) {
2049         create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2050         create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
2051     }
2052
2053     if (tag_sysmem) {
2054         create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2055                        machine->ram_size, "mach-virt.tag");
2056     }
2057
2058     vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
2059
2060     create_rtc(vms);
2061
2062     create_pcie(vms);
2063
2064     if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2065         vms->acpi_dev = create_acpi_ged(vms);
2066     } else {
2067         create_gpio_devices(vms, VIRT_GPIO, sysmem);
2068     }
2069
2070     if (vms->secure && !vmc->no_secure_gpio) {
2071         create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2072     }
2073
2074      /* connect powerdown request */
2075      vms->powerdown_notifier.notify = virt_powerdown_req;
2076      qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2077
2078     /* Create mmio transports, so the user can create virtio backends
2079      * (which will be automatically plugged in to the transports). If
2080      * no backend is created the transport will just sit harmlessly idle.
2081      */
2082     create_virtio_devices(vms);
2083
2084     vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2085     rom_set_fw(vms->fw_cfg);
2086
2087     create_platform_bus(vms);
2088
2089     if (machine->nvdimms_state->is_enabled) {
2090         const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2091             .space_id = AML_AS_SYSTEM_MEMORY,
2092             .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2093             .bit_width = NVDIMM_ACPI_IO_LEN << 3
2094         };
2095
2096         nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2097                                arm_virt_nvdimm_acpi_dsmio,
2098                                vms->fw_cfg, OBJECT(vms));
2099     }
2100
2101     vms->bootinfo.ram_size = machine->ram_size;
2102     vms->bootinfo.nb_cpus = smp_cpus;
2103     vms->bootinfo.board_id = -1;
2104     vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2105     vms->bootinfo.get_dtb = machvirt_dtb;
2106     vms->bootinfo.skip_dtb_autoload = true;
2107     vms->bootinfo.firmware_loaded = firmware_loaded;
2108     arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2109
2110     vms->machine_done.notify = virt_machine_done;
2111     qemu_add_machine_init_done_notifier(&vms->machine_done);
2112 }
2113
2114 static bool virt_get_secure(Object *obj, Error **errp)
2115 {
2116     VirtMachineState *vms = VIRT_MACHINE(obj);
2117
2118     return vms->secure;
2119 }
2120
2121 static void virt_set_secure(Object *obj, bool value, Error **errp)
2122 {
2123     VirtMachineState *vms = VIRT_MACHINE(obj);
2124
2125     vms->secure = value;
2126 }
2127
2128 static bool virt_get_virt(Object *obj, Error **errp)
2129 {
2130     VirtMachineState *vms = VIRT_MACHINE(obj);
2131
2132     return vms->virt;
2133 }
2134
2135 static void virt_set_virt(Object *obj, bool value, Error **errp)
2136 {
2137     VirtMachineState *vms = VIRT_MACHINE(obj);
2138
2139     vms->virt = value;
2140 }
2141
2142 static bool virt_get_highmem(Object *obj, Error **errp)
2143 {
2144     VirtMachineState *vms = VIRT_MACHINE(obj);
2145
2146     return vms->highmem;
2147 }
2148
2149 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2150 {
2151     VirtMachineState *vms = VIRT_MACHINE(obj);
2152
2153     vms->highmem = value;
2154 }
2155
2156 static bool virt_get_its(Object *obj, Error **errp)
2157 {
2158     VirtMachineState *vms = VIRT_MACHINE(obj);
2159
2160     return vms->its;
2161 }
2162
2163 static void virt_set_its(Object *obj, bool value, Error **errp)
2164 {
2165     VirtMachineState *vms = VIRT_MACHINE(obj);
2166
2167     vms->its = value;
2168 }
2169
2170 static char *virt_get_oem_id(Object *obj, Error **errp)
2171 {
2172     VirtMachineState *vms = VIRT_MACHINE(obj);
2173
2174     return g_strdup(vms->oem_id);
2175 }
2176
2177 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2178 {
2179     VirtMachineState *vms = VIRT_MACHINE(obj);
2180     size_t len = strlen(value);
2181
2182     if (len > 6) {
2183         error_setg(errp,
2184                    "User specified oem-id value is bigger than 6 bytes in size");
2185         return;
2186     }
2187
2188     strncpy(vms->oem_id, value, 6);
2189 }
2190
2191 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2192 {
2193     VirtMachineState *vms = VIRT_MACHINE(obj);
2194
2195     return g_strdup(vms->oem_table_id);
2196 }
2197
2198 static void virt_set_oem_table_id(Object *obj, const char *value,
2199                                   Error **errp)
2200 {
2201     VirtMachineState *vms = VIRT_MACHINE(obj);
2202     size_t len = strlen(value);
2203
2204     if (len > 8) {
2205         error_setg(errp,
2206                    "User specified oem-table-id value is bigger than 8 bytes in size");
2207         return;
2208     }
2209     strncpy(vms->oem_table_id, value, 8);
2210 }
2211
2212
2213 bool virt_is_acpi_enabled(VirtMachineState *vms)
2214 {
2215     if (vms->acpi == ON_OFF_AUTO_OFF) {
2216         return false;
2217     }
2218     return true;
2219 }
2220
2221 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2222                           void *opaque, Error **errp)
2223 {
2224     VirtMachineState *vms = VIRT_MACHINE(obj);
2225     OnOffAuto acpi = vms->acpi;
2226
2227     visit_type_OnOffAuto(v, name, &acpi, errp);
2228 }
2229
2230 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2231                           void *opaque, Error **errp)
2232 {
2233     VirtMachineState *vms = VIRT_MACHINE(obj);
2234
2235     visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2236 }
2237
2238 static bool virt_get_ras(Object *obj, Error **errp)
2239 {
2240     VirtMachineState *vms = VIRT_MACHINE(obj);
2241
2242     return vms->ras;
2243 }
2244
2245 static void virt_set_ras(Object *obj, bool value, Error **errp)
2246 {
2247     VirtMachineState *vms = VIRT_MACHINE(obj);
2248
2249     vms->ras = value;
2250 }
2251
2252 static bool virt_get_mte(Object *obj, Error **errp)
2253 {
2254     VirtMachineState *vms = VIRT_MACHINE(obj);
2255
2256     return vms->mte;
2257 }
2258
2259 static void virt_set_mte(Object *obj, bool value, Error **errp)
2260 {
2261     VirtMachineState *vms = VIRT_MACHINE(obj);
2262
2263     vms->mte = value;
2264 }
2265
2266 static char *virt_get_gic_version(Object *obj, Error **errp)
2267 {
2268     VirtMachineState *vms = VIRT_MACHINE(obj);
2269     const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
2270
2271     return g_strdup(val);
2272 }
2273
2274 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2275 {
2276     VirtMachineState *vms = VIRT_MACHINE(obj);
2277
2278     if (!strcmp(value, "3")) {
2279         vms->gic_version = VIRT_GIC_VERSION_3;
2280     } else if (!strcmp(value, "2")) {
2281         vms->gic_version = VIRT_GIC_VERSION_2;
2282     } else if (!strcmp(value, "host")) {
2283         vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2284     } else if (!strcmp(value, "max")) {
2285         vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2286     } else {
2287         error_setg(errp, "Invalid gic-version value");
2288         error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2289     }
2290 }
2291
2292 static char *virt_get_iommu(Object *obj, Error **errp)
2293 {
2294     VirtMachineState *vms = VIRT_MACHINE(obj);
2295
2296     switch (vms->iommu) {
2297     case VIRT_IOMMU_NONE:
2298         return g_strdup("none");
2299     case VIRT_IOMMU_SMMUV3:
2300         return g_strdup("smmuv3");
2301     default:
2302         g_assert_not_reached();
2303     }
2304 }
2305
2306 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2307 {
2308     VirtMachineState *vms = VIRT_MACHINE(obj);
2309
2310     if (!strcmp(value, "smmuv3")) {
2311         vms->iommu = VIRT_IOMMU_SMMUV3;
2312     } else if (!strcmp(value, "none")) {
2313         vms->iommu = VIRT_IOMMU_NONE;
2314     } else {
2315         error_setg(errp, "Invalid iommu value");
2316         error_append_hint(errp, "Valid values are none, smmuv3.\n");
2317     }
2318 }
2319
2320 static CpuInstanceProperties
2321 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2322 {
2323     MachineClass *mc = MACHINE_GET_CLASS(ms);
2324     const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2325
2326     assert(cpu_index < possible_cpus->len);
2327     return possible_cpus->cpus[cpu_index].props;
2328 }
2329
2330 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2331 {
2332     return idx % ms->numa_state->num_nodes;
2333 }
2334
2335 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2336 {
2337     int n;
2338     unsigned int max_cpus = ms->smp.max_cpus;
2339     VirtMachineState *vms = VIRT_MACHINE(ms);
2340
2341     if (ms->possible_cpus) {
2342         assert(ms->possible_cpus->len == max_cpus);
2343         return ms->possible_cpus;
2344     }
2345
2346     ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2347                                   sizeof(CPUArchId) * max_cpus);
2348     ms->possible_cpus->len = max_cpus;
2349     for (n = 0; n < ms->possible_cpus->len; n++) {
2350         ms->possible_cpus->cpus[n].type = ms->cpu_type;
2351         ms->possible_cpus->cpus[n].arch_id =
2352             virt_cpu_mp_affinity(vms, n);
2353         ms->possible_cpus->cpus[n].props.has_thread_id = true;
2354         ms->possible_cpus->cpus[n].props.thread_id = n;
2355     }
2356     return ms->possible_cpus;
2357 }
2358
2359 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2360                                  Error **errp)
2361 {
2362     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2363     const MachineState *ms = MACHINE(hotplug_dev);
2364     const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2365
2366     if (!vms->acpi_dev) {
2367         error_setg(errp,
2368                    "memory hotplug is not enabled: missing acpi-ged device");
2369         return;
2370     }
2371
2372     if (vms->mte) {
2373         error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2374         return;
2375     }
2376
2377     if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2378         error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2379         return;
2380     }
2381
2382     pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2383 }
2384
2385 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2386                              DeviceState *dev, Error **errp)
2387 {
2388     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2389     MachineState *ms = MACHINE(hotplug_dev);
2390     bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2391
2392     pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2393
2394     if (is_nvdimm) {
2395         nvdimm_plug(ms->nvdimms_state);
2396     }
2397
2398     hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2399                          dev, &error_abort);
2400 }
2401
2402 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2403                                             DeviceState *dev, Error **errp)
2404 {
2405     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2406
2407     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2408         virt_memory_pre_plug(hotplug_dev, dev, errp);
2409     } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2410         hwaddr db_start = 0, db_end = 0;
2411         char *resv_prop_str;
2412
2413         switch (vms->msi_controller) {
2414         case VIRT_MSI_CTRL_NONE:
2415             return;
2416         case VIRT_MSI_CTRL_ITS:
2417             /* GITS_TRANSLATER page */
2418             db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2419             db_end = base_memmap[VIRT_GIC_ITS].base +
2420                      base_memmap[VIRT_GIC_ITS].size - 1;
2421             break;
2422         case VIRT_MSI_CTRL_GICV2M:
2423             /* MSI_SETSPI_NS page */
2424             db_start = base_memmap[VIRT_GIC_V2M].base;
2425             db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2426             break;
2427         }
2428         resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2429                                         db_start, db_end,
2430                                         VIRTIO_IOMMU_RESV_MEM_T_MSI);
2431
2432         qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
2433         qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
2434         g_free(resv_prop_str);
2435     }
2436 }
2437
2438 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2439                                         DeviceState *dev, Error **errp)
2440 {
2441     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2442
2443     if (vms->platform_bus_dev) {
2444         MachineClass *mc = MACHINE_GET_CLASS(vms);
2445
2446         if (device_is_dynamic_sysbus(mc, dev)) {
2447             platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2448                                      SYS_BUS_DEVICE(dev));
2449         }
2450     }
2451     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2452         virt_memory_plug(hotplug_dev, dev, errp);
2453     }
2454     if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2455         PCIDevice *pdev = PCI_DEVICE(dev);
2456
2457         vms->iommu = VIRT_IOMMU_VIRTIO;
2458         vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2459         create_virtio_iommu_dt_bindings(vms);
2460     }
2461 }
2462
2463 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2464                                      DeviceState *dev, Error **errp)
2465 {
2466     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2467     Error *local_err = NULL;
2468
2469     if (!vms->acpi_dev) {
2470         error_setg(&local_err,
2471                    "memory hotplug is not enabled: missing acpi-ged device");
2472         goto out;
2473     }
2474
2475     if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2476         error_setg(&local_err,
2477                    "nvdimm device hot unplug is not supported yet.");
2478         goto out;
2479     }
2480
2481     hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2482                                    &local_err);
2483 out:
2484     error_propagate(errp, local_err);
2485 }
2486
2487 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2488                              DeviceState *dev, Error **errp)
2489 {
2490     VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2491     Error *local_err = NULL;
2492
2493     hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2494     if (local_err) {
2495         goto out;
2496     }
2497
2498     pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2499     qdev_unrealize(dev);
2500
2501 out:
2502     error_propagate(errp, local_err);
2503 }
2504
2505 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2506                                           DeviceState *dev, Error **errp)
2507 {
2508     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2509         virt_dimm_unplug_request(hotplug_dev, dev, errp);
2510     } else {
2511         error_setg(errp, "device unplug request for unsupported device"
2512                    " type: %s", object_get_typename(OBJECT(dev)));
2513     }
2514 }
2515
2516 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2517                                           DeviceState *dev, Error **errp)
2518 {
2519     if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2520         virt_dimm_unplug(hotplug_dev, dev, errp);
2521     } else {
2522         error_setg(errp, "virt: device unplug for unsupported device"
2523                    " type: %s", object_get_typename(OBJECT(dev)));
2524     }
2525 }
2526
2527 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2528                                                         DeviceState *dev)
2529 {
2530     MachineClass *mc = MACHINE_GET_CLASS(machine);
2531
2532     if (device_is_dynamic_sysbus(mc, dev) ||
2533        (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM))) {
2534         return HOTPLUG_HANDLER(machine);
2535     }
2536     if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2537         VirtMachineState *vms = VIRT_MACHINE(machine);
2538
2539         if (!vms->bootinfo.firmware_loaded || !virt_is_acpi_enabled(vms)) {
2540             return HOTPLUG_HANDLER(machine);
2541         }
2542     }
2543     return NULL;
2544 }
2545
2546 /*
2547  * for arm64 kvm_type [7-0] encodes the requested number of bits
2548  * in the IPA address space
2549  */
2550 static int virt_kvm_type(MachineState *ms, const char *type_str)
2551 {
2552     VirtMachineState *vms = VIRT_MACHINE(ms);
2553     int max_vm_pa_size, requested_pa_size;
2554     bool fixed_ipa;
2555
2556     max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
2557
2558     /* we freeze the memory map to compute the highest gpa */
2559     virt_set_memmap(vms);
2560
2561     requested_pa_size = 64 - clz64(vms->highest_gpa);
2562
2563     /*
2564      * KVM requires the IPA size to be at least 32 bits.
2565      */
2566     if (requested_pa_size < 32) {
2567         requested_pa_size = 32;
2568     }
2569
2570     if (requested_pa_size > max_vm_pa_size) {
2571         error_report("-m and ,maxmem option values "
2572                      "require an IPA range (%d bits) larger than "
2573                      "the one supported by the host (%d bits)",
2574                      requested_pa_size, max_vm_pa_size);
2575         exit(1);
2576     }
2577     /*
2578      * We return the requested PA log size, unless KVM only supports
2579      * the implicit legacy 40b IPA setting, in which case the kvm_type
2580      * must be 0.
2581      */
2582     return fixed_ipa ? 0 : requested_pa_size;
2583 }
2584
2585 static void virt_machine_class_init(ObjectClass *oc, void *data)
2586 {
2587     MachineClass *mc = MACHINE_CLASS(oc);
2588     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2589
2590     mc->init = machvirt_init;
2591     /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2592      * The value may be reduced later when we have more information about the
2593      * configuration of the particular instance.
2594      */
2595     mc->max_cpus = 512;
2596     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2597     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2598     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2599     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2600     machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2601     mc->block_default_type = IF_VIRTIO;
2602     mc->no_cdrom = 1;
2603     mc->pci_allow_0_address = true;
2604     /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2605     mc->minimum_page_bits = 12;
2606     mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2607     mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2608     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2609     mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2610     mc->kvm_type = virt_kvm_type;
2611     assert(!mc->get_hotplug_handler);
2612     mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2613     hc->pre_plug = virt_machine_device_pre_plug_cb;
2614     hc->plug = virt_machine_device_plug_cb;
2615     hc->unplug_request = virt_machine_device_unplug_request_cb;
2616     hc->unplug = virt_machine_device_unplug_cb;
2617     mc->nvdimm_supported = true;
2618     mc->auto_enable_numa_with_memhp = true;
2619     mc->auto_enable_numa_with_memdev = true;
2620     mc->default_ram_id = "mach-virt.ram";
2621
2622     object_class_property_add(oc, "acpi", "OnOffAuto",
2623         virt_get_acpi, virt_set_acpi,
2624         NULL, NULL);
2625     object_class_property_set_description(oc, "acpi",
2626         "Enable ACPI");
2627     object_class_property_add_bool(oc, "secure", virt_get_secure,
2628                                    virt_set_secure);
2629     object_class_property_set_description(oc, "secure",
2630                                                 "Set on/off to enable/disable the ARM "
2631                                                 "Security Extensions (TrustZone)");
2632
2633     object_class_property_add_bool(oc, "virtualization", virt_get_virt,
2634                                    virt_set_virt);
2635     object_class_property_set_description(oc, "virtualization",
2636                                           "Set on/off to enable/disable emulating a "
2637                                           "guest CPU which implements the ARM "
2638                                           "Virtualization Extensions");
2639
2640     object_class_property_add_bool(oc, "highmem", virt_get_highmem,
2641                                    virt_set_highmem);
2642     object_class_property_set_description(oc, "highmem",
2643                                           "Set on/off to enable/disable using "
2644                                           "physical address space above 32 bits");
2645
2646     object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
2647                                   virt_set_gic_version);
2648     object_class_property_set_description(oc, "gic-version",
2649                                           "Set GIC version. "
2650                                           "Valid values are 2, 3, host and max");
2651
2652     object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
2653     object_class_property_set_description(oc, "iommu",
2654                                           "Set the IOMMU type. "
2655                                           "Valid values are none and smmuv3");
2656
2657     object_class_property_add_bool(oc, "ras", virt_get_ras,
2658                                    virt_set_ras);
2659     object_class_property_set_description(oc, "ras",
2660                                           "Set on/off to enable/disable reporting host memory errors "
2661                                           "to a KVM guest using ACPI and guest external abort exceptions");
2662
2663     object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
2664     object_class_property_set_description(oc, "mte",
2665                                           "Set on/off to enable/disable emulating a "
2666                                           "guest CPU which implements the ARM "
2667                                           "Memory Tagging Extension");
2668
2669     object_class_property_add_bool(oc, "its", virt_get_its,
2670                                    virt_set_its);
2671     object_class_property_set_description(oc, "its",
2672                                           "Set on/off to enable/disable "
2673                                           "ITS instantiation");
2674
2675     object_class_property_add_str(oc, "x-oem-id",
2676                                   virt_get_oem_id,
2677                                   virt_set_oem_id);
2678     object_class_property_set_description(oc, "x-oem-id",
2679                                           "Override the default value of field OEMID "
2680                                           "in ACPI table header."
2681                                           "The string may be up to 6 bytes in size");
2682
2683
2684     object_class_property_add_str(oc, "x-oem-table-id",
2685                                   virt_get_oem_table_id,
2686                                   virt_set_oem_table_id);
2687     object_class_property_set_description(oc, "x-oem-table-id",
2688                                           "Override the default value of field OEM Table ID "
2689                                           "in ACPI table header."
2690                                           "The string may be up to 8 bytes in size");
2691
2692 }
2693
2694 static void virt_instance_init(Object *obj)
2695 {
2696     VirtMachineState *vms = VIRT_MACHINE(obj);
2697     VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
2698
2699     /* EL3 is disabled by default on virt: this makes us consistent
2700      * between KVM and TCG for this board, and it also allows us to
2701      * boot UEFI blobs which assume no TrustZone support.
2702      */
2703     vms->secure = false;
2704
2705     /* EL2 is also disabled by default, for similar reasons */
2706     vms->virt = false;
2707
2708     /* High memory is enabled by default */
2709     vms->highmem = true;
2710     vms->gic_version = VIRT_GIC_VERSION_NOSEL;
2711
2712     vms->highmem_ecam = !vmc->no_highmem_ecam;
2713
2714     if (vmc->no_its) {
2715         vms->its = false;
2716     } else {
2717         /* Default allows ITS instantiation */
2718         vms->its = true;
2719     }
2720
2721     /* Default disallows iommu instantiation */
2722     vms->iommu = VIRT_IOMMU_NONE;
2723
2724     /* Default disallows RAS instantiation */
2725     vms->ras = false;
2726
2727     /* MTE is disabled by default.  */
2728     vms->mte = false;
2729
2730     vms->irqmap = a15irqmap;
2731
2732     virt_flash_create(vms);
2733
2734     vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
2735     vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
2736 }
2737
2738 static const TypeInfo virt_machine_info = {
2739     .name          = TYPE_VIRT_MACHINE,
2740     .parent        = TYPE_MACHINE,
2741     .abstract      = true,
2742     .instance_size = sizeof(VirtMachineState),
2743     .class_size    = sizeof(VirtMachineClass),
2744     .class_init    = virt_machine_class_init,
2745     .instance_init = virt_instance_init,
2746     .interfaces = (InterfaceInfo[]) {
2747          { TYPE_HOTPLUG_HANDLER },
2748          { }
2749     },
2750 };
2751
2752 static void machvirt_machine_init(void)
2753 {
2754     type_register_static(&virt_machine_info);
2755 }
2756 type_init(machvirt_machine_init);
2757
2758 static void virt_machine_6_1_options(MachineClass *mc)
2759 {
2760 }
2761 DEFINE_VIRT_MACHINE_AS_LATEST(6, 1)
2762
2763 static void virt_machine_6_0_options(MachineClass *mc)
2764 {
2765 }
2766 DEFINE_VIRT_MACHINE(6, 0)
2767
2768 static void virt_machine_5_2_options(MachineClass *mc)
2769 {
2770     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2771
2772     virt_machine_6_0_options(mc);
2773     compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
2774     vmc->no_secure_gpio = true;
2775 }
2776 DEFINE_VIRT_MACHINE(5, 2)
2777
2778 static void virt_machine_5_1_options(MachineClass *mc)
2779 {
2780     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2781
2782     virt_machine_5_2_options(mc);
2783     compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
2784     vmc->no_kvm_steal_time = true;
2785 }
2786 DEFINE_VIRT_MACHINE(5, 1)
2787
2788 static void virt_machine_5_0_options(MachineClass *mc)
2789 {
2790     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2791
2792     virt_machine_5_1_options(mc);
2793     compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
2794     mc->numa_mem_supported = true;
2795     vmc->acpi_expose_flash = true;
2796     mc->auto_enable_numa_with_memdev = false;
2797 }
2798 DEFINE_VIRT_MACHINE(5, 0)
2799
2800 static void virt_machine_4_2_options(MachineClass *mc)
2801 {
2802     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2803
2804     virt_machine_5_0_options(mc);
2805     compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
2806     vmc->kvm_no_adjvtime = true;
2807 }
2808 DEFINE_VIRT_MACHINE(4, 2)
2809
2810 static void virt_machine_4_1_options(MachineClass *mc)
2811 {
2812     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2813
2814     virt_machine_4_2_options(mc);
2815     compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
2816     vmc->no_ged = true;
2817     mc->auto_enable_numa_with_memhp = false;
2818 }
2819 DEFINE_VIRT_MACHINE(4, 1)
2820
2821 static void virt_machine_4_0_options(MachineClass *mc)
2822 {
2823     virt_machine_4_1_options(mc);
2824     compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2825 }
2826 DEFINE_VIRT_MACHINE(4, 0)
2827
2828 static void virt_machine_3_1_options(MachineClass *mc)
2829 {
2830     virt_machine_4_0_options(mc);
2831     compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2832 }
2833 DEFINE_VIRT_MACHINE(3, 1)
2834
2835 static void virt_machine_3_0_options(MachineClass *mc)
2836 {
2837     virt_machine_3_1_options(mc);
2838     compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2839 }
2840 DEFINE_VIRT_MACHINE(3, 0)
2841
2842 static void virt_machine_2_12_options(MachineClass *mc)
2843 {
2844     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2845
2846     virt_machine_3_0_options(mc);
2847     compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2848     vmc->no_highmem_ecam = true;
2849     mc->max_cpus = 255;
2850 }
2851 DEFINE_VIRT_MACHINE(2, 12)
2852
2853 static void virt_machine_2_11_options(MachineClass *mc)
2854 {
2855     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2856
2857     virt_machine_2_12_options(mc);
2858     compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2859     vmc->smbios_old_sys_ver = true;
2860 }
2861 DEFINE_VIRT_MACHINE(2, 11)
2862
2863 static void virt_machine_2_10_options(MachineClass *mc)
2864 {
2865     virt_machine_2_11_options(mc);
2866     compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2867     /* before 2.11 we never faulted accesses to bad addresses */
2868     mc->ignore_memory_transaction_failures = true;
2869 }
2870 DEFINE_VIRT_MACHINE(2, 10)
2871
2872 static void virt_machine_2_9_options(MachineClass *mc)
2873 {
2874     virt_machine_2_10_options(mc);
2875     compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2876 }
2877 DEFINE_VIRT_MACHINE(2, 9)
2878
2879 static void virt_machine_2_8_options(MachineClass *mc)
2880 {
2881     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2882
2883     virt_machine_2_9_options(mc);
2884     compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
2885     /* For 2.8 and earlier we falsely claimed in the DT that
2886      * our timers were edge-triggered, not level-triggered.
2887      */
2888     vmc->claim_edge_triggered_timers = true;
2889 }
2890 DEFINE_VIRT_MACHINE(2, 8)
2891
2892 static void virt_machine_2_7_options(MachineClass *mc)
2893 {
2894     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2895
2896     virt_machine_2_8_options(mc);
2897     compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2898     /* ITS was introduced with 2.8 */
2899     vmc->no_its = true;
2900     /* Stick with 1K pages for migration compatibility */
2901     mc->minimum_page_bits = 0;
2902 }
2903 DEFINE_VIRT_MACHINE(2, 7)
2904
2905 static void virt_machine_2_6_options(MachineClass *mc)
2906 {
2907     VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2908
2909     virt_machine_2_7_options(mc);
2910     compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
2911     vmc->disallow_affinity_adjustment = true;
2912     /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2913     vmc->no_pmu = true;
2914 }
2915 DEFINE_VIRT_MACHINE(2, 6)