4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #define DATA_TYPE uint64_t
27 #define DATA_TYPE uint32_t
31 #define DATA_TYPE uint16_t
32 #define DATA_STYPE int16_t
36 #define DATA_TYPE uint8_t
37 #define DATA_STYPE int8_t
39 #error unsupported data size
44 #define CPU_MEM_INDEX 0
45 #define MMUSUFFIX _mmu
47 #elif ACCESS_TYPE == 1
49 #define CPU_MEM_INDEX 1
50 #define MMUSUFFIX _mmu
52 #elif ACCESS_TYPE == 2
55 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
56 #elif defined (TARGET_PPC)
57 #define CPU_MEM_INDEX (msr_pr)
58 #elif defined (TARGET_SPARC)
59 #define CPU_MEM_INDEX ((env->psrs) == 0)
61 #define MMUSUFFIX _mmu
63 #elif ACCESS_TYPE == 3
66 #define CPU_MEM_INDEX ((env->hflags & HF_CPL_MASK) == 3)
67 #elif defined (TARGET_PPC)
68 #define CPU_MEM_INDEX (msr_pr)
69 #elif defined (TARGET_SPARC)
70 #define CPU_MEM_INDEX ((env->psrs) == 0)
72 #define MMUSUFFIX _cmmu
75 #error invalid ACCESS_TYPE
79 #define RES_TYPE uint64_t
85 DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(unsigned long addr,
87 void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(unsigned long addr, DATA_TYPE v, int is_user);
89 #if (DATA_SIZE <= 4) && defined(__i386__) && (ACCESS_TYPE <= 1) && defined(ASM_SOFTMMU)
91 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(void *ptr)
95 asm volatile ("movl %1, %%edx\n"
100 "leal %5(%%edx, %%ebp), %%edx\n"
101 "cmpl (%%edx), %%eax\n"
110 "addl 4(%%edx), %%eax\n"
112 "movzbl (%%eax), %0\n"
114 "movzwl (%%eax), %0\n"
118 #error unsupported size
123 "i" ((CPU_TLB_SIZE - 1) << 3),
124 "i" (TARGET_PAGE_BITS - 3),
125 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
126 "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
128 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
129 : "%eax", "%ecx", "%edx", "memory", "cc");
134 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(void *ptr)
138 asm volatile ("movl %1, %%edx\n"
143 "leal %5(%%edx, %%ebp), %%edx\n"
144 "cmpl (%%edx), %%eax\n"
155 #error unsupported size
159 "addl 4(%%edx), %%eax\n"
161 "movsbl (%%eax), %0\n"
163 "movswl (%%eax), %0\n"
165 #error unsupported size
170 "i" ((CPU_TLB_SIZE - 1) << 3),
171 "i" (TARGET_PAGE_BITS - 3),
172 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
173 "m" (*(uint32_t *)offsetof(CPUState, tlb_read[CPU_MEM_INDEX][0].address)),
175 "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
176 : "%eax", "%ecx", "%edx", "memory", "cc");
181 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(void *ptr, RES_TYPE v)
183 asm volatile ("movl %0, %%edx\n"
188 "leal %5(%%edx, %%ebp), %%edx\n"
189 "cmpl (%%edx), %%eax\n"
193 "movzbl %b1, %%edx\n"
195 "movzwl %w1, %%edx\n"
199 #error unsupported size
206 "addl 4(%%edx), %%eax\n"
208 "movb %b1, (%%eax)\n"
210 "movw %w1, (%%eax)\n"
214 #error unsupported size
219 /* NOTE: 'q' would be needed as constraint, but we could not use it
222 "i" ((CPU_TLB_SIZE - 1) << 3),
223 "i" (TARGET_PAGE_BITS - 3),
224 "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
225 "m" (*(uint32_t *)offsetof(CPUState, tlb_write[CPU_MEM_INDEX][0].address)),
227 "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
228 : "%eax", "%ecx", "%edx", "memory", "cc");
233 /* generic load/store macros */
235 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(void *ptr)
239 unsigned long addr, physaddr;
242 addr = (unsigned long)ptr;
243 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
244 is_user = CPU_MEM_INDEX;
245 if (__builtin_expect(env->tlb_read[is_user][index].address !=
246 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
247 res = glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
249 physaddr = addr + env->tlb_read[is_user][index].addend;
250 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)physaddr);
256 static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(void *ptr)
259 unsigned long addr, physaddr;
262 addr = (unsigned long)ptr;
263 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
264 is_user = CPU_MEM_INDEX;
265 if (__builtin_expect(env->tlb_read[is_user][index].address !=
266 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
267 res = (DATA_STYPE)glue(glue(__ld, SUFFIX), MMUSUFFIX)(addr, is_user);
269 physaddr = addr + env->tlb_read[is_user][index].addend;
270 res = glue(glue(lds, SUFFIX), _raw)((uint8_t *)physaddr);
276 /* generic store macro */
278 static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(void *ptr, RES_TYPE v)
281 unsigned long addr, physaddr;
284 addr = (unsigned long)ptr;
285 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
286 is_user = CPU_MEM_INDEX;
287 if (__builtin_expect(env->tlb_write[is_user][index].address !=
288 (addr & (TARGET_PAGE_MASK | (DATA_SIZE - 1))), 0)) {
289 glue(glue(__st, SUFFIX), MMUSUFFIX)(addr, v, is_user);
291 physaddr = addr + env->tlb_write[is_user][index].addend;
292 glue(glue(st, SUFFIX), _raw)((uint8_t *)physaddr, v);
299 static inline double glue(ldfq, MEMSUFFIX)(void *ptr)
305 u.i = glue(ldq, MEMSUFFIX)(ptr);
309 static inline void glue(stfq, MEMSUFFIX)(void *ptr, double v)
316 glue(stq, MEMSUFFIX)(ptr, u.i);
318 #endif /* DATA_SIZE == 8 */
321 static inline float glue(ldfl, MEMSUFFIX)(void *ptr)
327 u.i = glue(ldl, MEMSUFFIX)(ptr);
331 static inline void glue(stfl, MEMSUFFIX)(void *ptr, float v)
338 glue(stl, MEMSUFFIX)(ptr, u.i);
340 #endif /* DATA_SIZE == 4 */