hw/pci-host/piix.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/isa/isa.h"
  30 #include "hw/sysbus.h"
  31 #include "qemu/range.h"
  32 #include "hw/xen/xen.h"
  33 #include "hw/pci-host/pam.h"
  34 #include "sysemu/sysemu.h"
  35 #include "hw/i386/ioapic.h"
  36 #include "qapi/visitor.h"
  37
  38 /*
  39  * I440FX chipset data sheet.
  40  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  41  */
  42
  43 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
  44 #define I440FX_PCI_HOST_BRIDGE(obj) \
  45     OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
  46
  47 typedef struct I440FXState {
  48     PCIHostState parent_obj;
  49     PcPciInfo pci_info;
  50     uint64_t pci_hole64_size;
  51     uint32_t short_root_bus;
  52 } I440FXState;
  53
  54 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  55 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  56 #define XEN_PIIX_NUM_PIRQS      128ULL
  57 #define PIIX_PIRQC              0x60
  58
  59 /*
  60  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  61  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  62  */
  63 #define RCR_IOPORT 0xcf9
  64
  65 typedef struct PIIX3State {
  66     PCIDevice dev;
  67
  68     /*
  69      * bitmap to track pic levels.
  70      * The pic level is the logical OR of all the PCI irqs mapped to it
  71      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  72      *
  73      * PIRQ is mapped to PIC pins, we track it by
  74      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  75      * pic_irq * PIIX_NUM_PIRQS + pirq
  76      */
  77 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  78 #error "unable to encode pic state in 64bit in pic_levels."
  79 #endif
  80     uint64_t pic_levels;
  81
  82     qemu_irq *pic;
  83
  84     /* This member isn't used. Just for save/load compatibility */
  85     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  86
  87     /* Reset Control Register contents */
  88     uint8_t rcr;
  89
  90     /* IO memory region for Reset Control Register (RCR_IOPORT) */
  91     MemoryRegion rcr_mem;
  92 } PIIX3State;
  93
  94 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
  95 #define PIIX3_PCI_DEVICE(obj) \
  96     OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
  97
  98 #define TYPE_I440FX_PCI_DEVICE "i440FX"
  99 #define I440FX_PCI_DEVICE(obj) \
 100     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
 101
 102 struct PCII440FXState {
 103     /*< private >*/
 104     PCIDevice parent_obj;
 105     /*< public >*/
 106
 107     MemoryRegion *system_memory;
 108     MemoryRegion *pci_address_space;
 109     MemoryRegion *ram_memory;
 110     PAMMemoryRegion pam_regions[13];
 111     MemoryRegion smram_region;
 112     MemoryRegion smram, low_smram;
 113 };
 114
 115
 116 #define I440FX_PAM      0x59
 117 #define I440FX_PAM_SIZE 7
 118 #define I440FX_SMRAM    0x72
 119
 120 /* Older coreboot versions (4.0 and older) read a config register that doesn't
 121  * exist in real hardware, to get the RAM size from QEMU.
 122  */
 123 #define I440FX_COREBOOT_RAM_SIZE 0x57
 124
 125 static void piix3_set_irq(void *opaque, int pirq, int level);
 126 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 127 static void piix3_write_config_xen(PCIDevice *dev,
 128                                uint32_t address, uint32_t val, int len);
 129
 130 /* return the global irq number corresponding to a given device irq
 131    pin. We could also use the bus number to have a more precise
 132    mapping. */
 133 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 134 {
 135     int slot_addend;
 136     slot_addend = (pci_dev->devfn >> 3) - 1;
 137     return (pci_intx + slot_addend) & 3;
 138 }
 139
 140 static void i440fx_update_memory_mappings(PCII440FXState *d)
 141 {
 142     int i;
 143     PCIDevice *pd = PCI_DEVICE(d);
 144
 145     memory_region_transaction_begin();
 146     for (i = 0; i < 13; i++) {
 147         pam_update(&d->pam_regions[i], i,
 148                    pd->config[I440FX_PAM + ((i + 1) / 2)]);
 149     }
 150     memory_region_set_enabled(&d->smram_region,
 151                               !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
 152     memory_region_set_enabled(&d->smram,
 153                               pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
 154     memory_region_transaction_commit();
 155 }
 156
 157
 158 static void i440fx_write_config(PCIDevice *dev,
 159                                 uint32_t address, uint32_t val, int len)
 160 {
 161     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 162
 163     /* XXX: implement SMRAM.D_LOCK */
 164     pci_default_write_config(dev, address, val, len);
 165     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 166         range_covers_byte(address, len, I440FX_SMRAM)) {
 167         i440fx_update_memory_mappings(d);
 168     }
 169 }
 170
 171 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 172 {
 173     PCII440FXState *d = opaque;
 174     PCIDevice *pd = PCI_DEVICE(d);
 175     int ret, i;
 176     uint8_t smm_enabled;
 177
 178     ret = pci_device_load(pd, f);
 179     if (ret < 0)
 180         return ret;
 181     i440fx_update_memory_mappings(d);
 182     qemu_get_8s(f, &smm_enabled);
 183
 184     if (version_id == 2) {
 185         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 186             qemu_get_be32(f); /* dummy load for compatibility */
 187         }
 188     }
 189
 190     return 0;
 191 }
 192
 193 static int i440fx_post_load(void *opaque, int version_id)
 194 {
 195     PCII440FXState *d = opaque;
 196
 197     i440fx_update_memory_mappings(d);
 198     return 0;
 199 }
 200
 201 static const VMStateDescription vmstate_i440fx = {
 202     .name = "I440FX",
 203     .version_id = 3,
 204     .minimum_version_id = 3,
 205     .minimum_version_id_old = 1,
 206     .load_state_old = i440fx_load_old,
 207     .post_load = i440fx_post_load,
 208     .fields = (VMStateField[]) {
 209         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 210         /* Used to be smm_enabled, which was basically always zero because
 211          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 212          */
 213         VMSTATE_UNUSED(1),
 214         VMSTATE_END_OF_LIST()
 215     }
 216 };
 217
 218 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
 219                                               void *opaque, const char *name,
 220                                               Error **errp)
 221 {
 222     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 223     uint32_t value = s->pci_info.w32.begin;
 224
 225     visit_type_uint32(v, &value, name, errp);
 226 }
 227
 228 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
 229                                             void *opaque, const char *name,
 230                                             Error **errp)
 231 {
 232     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 233     uint32_t value = s->pci_info.w32.end;
 234
 235     visit_type_uint32(v, &value, name, errp);
 236 }
 237
 238 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
 239                                                 void *opaque, const char *name,
 240                                                 Error **errp)
 241 {
 242     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 243     Range w64;
 244
 245     pci_bus_get_w64_range(h->bus, &w64);
 246
 247     visit_type_uint64(v, &w64.begin, name, errp);
 248 }
 249
 250 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 251                                               void *opaque, const char *name,
 252                                               Error **errp)
 253 {
 254     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 255     Range w64;
 256
 257     pci_bus_get_w64_range(h->bus, &w64);
 258
 259     visit_type_uint64(v, &w64.end, name, errp);
 260 }
 261
 262 static void i440fx_pcihost_initfn(Object *obj)
 263 {
 264     PCIHostState *s = PCI_HOST_BRIDGE(obj);
 265     I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj);
 266
 267     memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 268                           "pci-conf-idx", 4);
 269     memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 270                           "pci-conf-data", 4);
 271
 272     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
 273                         i440fx_pcihost_get_pci_hole_start,
 274                         NULL, NULL, NULL, NULL);
 275
 276     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
 277                         i440fx_pcihost_get_pci_hole_end,
 278                         NULL, NULL, NULL, NULL);
 279
 280     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
 281                         i440fx_pcihost_get_pci_hole64_start,
 282                         NULL, NULL, NULL, NULL);
 283
 284     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
 285                         i440fx_pcihost_get_pci_hole64_end,
 286                         NULL, NULL, NULL, NULL);
 287
 288     d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
 289 }
 290
 291 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 292 {
 293     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 294     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 295
 296     sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 297     sysbus_init_ioports(sbd, 0xcf8, 4);
 298
 299     sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 300     sysbus_init_ioports(sbd, 0xcfc, 4);
 301 }
 302
 303 static void i440fx_realize(PCIDevice *dev, Error **errp)
 304 {
 305     dev->config[I440FX_SMRAM] = 0x02;
 306 }
 307
 308 PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
 309                     int *piix3_devfn,
 310                     ISABus **isa_bus, qemu_irq *pic,
 311                     MemoryRegion *address_space_mem,
 312                     MemoryRegion *address_space_io,
 313                     ram_addr_t ram_size,
 314                     ram_addr_t below_4g_mem_size,
 315                     ram_addr_t above_4g_mem_size,
 316                     MemoryRegion *pci_address_space,
 317                     MemoryRegion *ram_memory)
 318 {
 319     DeviceState *dev;
 320     PCIBus *b;
 321     PCIDevice *d;
 322     PCIHostState *s;
 323     PIIX3State *piix3;
 324     PCII440FXState *f;
 325     unsigned i;
 326     I440FXState *i440fx;
 327
 328     dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
 329     s = PCI_HOST_BRIDGE(dev);
 330     b = pci_bus_new(dev, NULL, pci_address_space,
 331                     address_space_io, 0, TYPE_PCI_BUS);
 332     s->bus = b;
 333     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 334     qdev_init_nofail(dev);
 335
 336     d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
 337     *pi440fx_state = I440FX_PCI_DEVICE(d);
 338     f = *pi440fx_state;
 339     f->system_memory = address_space_mem;
 340     f->pci_address_space = pci_address_space;
 341     f->ram_memory = ram_memory;
 342
 343     i440fx = I440FX_PCI_HOST_BRIDGE(dev);
 344     i440fx->pci_info.w32.begin = below_4g_mem_size;
 345
 346     /* setup pci memory mapping */
 347     pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
 348                            f->pci_address_space);
 349
 350     /* if *disabled* show SMRAM to all CPUs */
 351     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 352                              f->pci_address_space, 0xa0000, 0x20000);
 353     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 354                                         &f->smram_region, 1);
 355     memory_region_set_enabled(&f->smram_region, true);
 356
 357     /* smram, as seen by SMM CPUs */
 358     memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
 359     memory_region_set_enabled(&f->smram, true);
 360     memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
 361                              f->ram_memory, 0xa0000, 0x20000);
 362     memory_region_set_enabled(&f->low_smram, true);
 363     memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
 364     object_property_add_const_link(qdev_get_machine(), "smram",
 365                                    OBJECT(&f->smram), &error_abort);
 366
 367     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 368              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 369     for (i = 0; i < 12; ++i) {
 370         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 371                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 372                  PAM_EXPAN_SIZE);
 373     }
 374
 375     /* Xen supports additional interrupt routes from the PCI devices to
 376      * the IOAPIC: the four pins of each PCI device on the bus are also
 377      * connected to the IOAPIC directly.
 378      * These additional routes can be discovered through ACPI. */
 379     if (xen_enabled()) {
 380         PCIDevice *pci_dev = pci_create_simple_multifunction(b,
 381                              -1, true, "PIIX3-xen");
 382         piix3 = PIIX3_PCI_DEVICE(pci_dev);
 383         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 384                 piix3, XEN_PIIX_NUM_PIRQS);
 385     } else {
 386         PCIDevice *pci_dev = pci_create_simple_multifunction(b,
 387                              -1, true, "PIIX3");
 388         piix3 = PIIX3_PCI_DEVICE(pci_dev);
 389         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 390                 PIIX_NUM_PIRQS);
 391         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 392     }
 393     piix3->pic = pic;
 394     *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
 395
 396     *piix3_devfn = piix3->dev.devfn;
 397
 398     ram_size = ram_size / 8 / 1024 / 1024;
 399     if (ram_size > 255) {
 400         ram_size = 255;
 401     }
 402     d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
 403
 404     i440fx_update_memory_mappings(f);
 405
 406     return b;
 407 }
 408
 409 PCIBus *find_i440fx(void)
 410 {
 411     PCIHostState *s = OBJECT_CHECK(PCIHostState,
 412                                    object_resolve_path("/machine/i440fx", NULL),
 413                                    TYPE_PCI_HOST_BRIDGE);
 414     return s ? s->bus : NULL;
 415 }
 416
 417 /* PIIX3 PCI to ISA bridge */
 418 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 419 {
 420     qemu_set_irq(piix3->pic[pic_irq],
 421                  !!(piix3->pic_levels &
 422                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 423                      (pic_irq * PIIX_NUM_PIRQS))));
 424 }
 425
 426 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
 427 {
 428     int pic_irq;
 429     uint64_t mask;
 430
 431     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 432     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 433         return;
 434     }
 435
 436     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 437     piix3->pic_levels &= ~mask;
 438     piix3->pic_levels |= mask * !!level;
 439 }
 440
 441 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 442 {
 443     int pic_irq;
 444
 445     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 446     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 447         return;
 448     }
 449
 450     piix3_set_irq_level_internal(piix3, pirq, level);
 451
 452     piix3_set_irq_pic(piix3, pic_irq);
 453 }
 454
 455 static void piix3_set_irq(void *opaque, int pirq, int level)
 456 {
 457     PIIX3State *piix3 = opaque;
 458     piix3_set_irq_level(piix3, pirq, level);
 459 }
 460
 461 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 462 {
 463     PIIX3State *piix3 = opaque;
 464     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 465     PCIINTxRoute route;
 466
 467     if (irq < PIIX_NUM_PIC_IRQS) {
 468         route.mode = PCI_INTX_ENABLED;
 469         route.irq = irq;
 470     } else {
 471         route.mode = PCI_INTX_DISABLED;
 472         route.irq = -1;
 473     }
 474     return route;
 475 }
 476
 477 /* irq routing is changed. so rebuild bitmap */
 478 static void piix3_update_irq_levels(PIIX3State *piix3)
 479 {
 480     int pirq;
 481
 482     piix3->pic_levels = 0;
 483     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 484         piix3_set_irq_level(piix3, pirq,
 485                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 486     }
 487 }
 488
 489 static void piix3_write_config(PCIDevice *dev,
 490                                uint32_t address, uint32_t val, int len)
 491 {
 492     pci_default_write_config(dev, address, val, len);
 493     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 494         PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
 495         int pic_irq;
 496
 497         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 498         piix3_update_irq_levels(piix3);
 499         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 500             piix3_set_irq_pic(piix3, pic_irq);
 501         }
 502     }
 503 }
 504
 505 static void piix3_write_config_xen(PCIDevice *dev,
 506                                uint32_t address, uint32_t val, int len)
 507 {
 508     xen_piix_pci_write_config_client(address, val, len);
 509     piix3_write_config(dev, address, val, len);
 510 }
 511
 512 static void piix3_reset(void *opaque)
 513 {
 514     PIIX3State *d = opaque;
 515     uint8_t *pci_conf = d->dev.config;
 516
 517     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 518     pci_conf[0x05] = 0x00;
 519     pci_conf[0x06] = 0x00;
 520     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 521     pci_conf[0x4c] = 0x4d;
 522     pci_conf[0x4e] = 0x03;
 523     pci_conf[0x4f] = 0x00;
 524     pci_conf[0x60] = 0x80;
 525     pci_conf[0x61] = 0x80;
 526     pci_conf[0x62] = 0x80;
 527     pci_conf[0x63] = 0x80;
 528     pci_conf[0x69] = 0x02;
 529     pci_conf[0x70] = 0x80;
 530     pci_conf[0x76] = 0x0c;
 531     pci_conf[0x77] = 0x0c;
 532     pci_conf[0x78] = 0x02;
 533     pci_conf[0x79] = 0x00;
 534     pci_conf[0x80] = 0x00;
 535     pci_conf[0x82] = 0x00;
 536     pci_conf[0xa0] = 0x08;
 537     pci_conf[0xa2] = 0x00;
 538     pci_conf[0xa3] = 0x00;
 539     pci_conf[0xa4] = 0x00;
 540     pci_conf[0xa5] = 0x00;
 541     pci_conf[0xa6] = 0x00;
 542     pci_conf[0xa7] = 0x00;
 543     pci_conf[0xa8] = 0x0f;
 544     pci_conf[0xaa] = 0x00;
 545     pci_conf[0xab] = 0x00;
 546     pci_conf[0xac] = 0x00;
 547     pci_conf[0xae] = 0x00;
 548
 549     d->pic_levels = 0;
 550     d->rcr = 0;
 551 }
 552
 553 static int piix3_post_load(void *opaque, int version_id)
 554 {
 555     PIIX3State *piix3 = opaque;
 556     int pirq;
 557
 558     /* Because the i8259 has not been deserialized yet, qemu_irq_raise
 559      * might bring the system to a different state than the saved one;
 560      * for example, the interrupt could be masked but the i8259 would
 561      * not know that yet and would trigger an interrupt in the CPU.
 562      *
 563      * Here, we update irq levels without raising the interrupt.
 564      * Interrupt state will be deserialized separately through the i8259.
 565      */
 566     piix3->pic_levels = 0;
 567     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 568         piix3_set_irq_level_internal(piix3, pirq,
 569                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 570     }
 571     return 0;
 572 }
 573
 574 static void piix3_pre_save(void *opaque)
 575 {
 576     int i;
 577     PIIX3State *piix3 = opaque;
 578
 579     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 580         piix3->pci_irq_levels_vmstate[i] =
 581             pci_bus_get_irq_level(piix3->dev.bus, i);
 582     }
 583 }
 584
 585 static bool piix3_rcr_needed(void *opaque)
 586 {
 587     PIIX3State *piix3 = opaque;
 588
 589     return (piix3->rcr != 0);
 590 }
 591
 592 static const VMStateDescription vmstate_piix3_rcr = {
 593     .name = "PIIX3/rcr",
 594     .version_id = 1,
 595     .minimum_version_id = 1,
 596     .needed = piix3_rcr_needed,
 597     .fields = (VMStateField[]) {
 598         VMSTATE_UINT8(rcr, PIIX3State),
 599         VMSTATE_END_OF_LIST()
 600     }
 601 };
 602
 603 static const VMStateDescription vmstate_piix3 = {
 604     .name = "PIIX3",
 605     .version_id = 3,
 606     .minimum_version_id = 2,
 607     .post_load = piix3_post_load,
 608     .pre_save = piix3_pre_save,
 609     .fields = (VMStateField[]) {
 610         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 611         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 612                               PIIX_NUM_PIRQS, 3),
 613         VMSTATE_END_OF_LIST()
 614     },
 615     .subsections = (const VMStateDescription*[]) {
 616         &vmstate_piix3_rcr,
 617         NULL
 618     }
 619 };
 620
 621
 622 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 623 {
 624     PIIX3State *d = opaque;
 625
 626     if (val & 4) {
 627         qemu_system_reset_request();
 628         return;
 629     }
 630     d->rcr = val & 2; /* keep System Reset type only */
 631 }
 632
 633 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 634 {
 635     PIIX3State *d = opaque;
 636
 637     return d->rcr;
 638 }
 639
 640 static const MemoryRegionOps rcr_ops = {
 641     .read = rcr_read,
 642     .write = rcr_write,
 643     .endianness = DEVICE_LITTLE_ENDIAN
 644 };
 645
 646 static void piix3_realize(PCIDevice *dev, Error **errp)
 647 {
 648     PIIX3State *d = PIIX3_PCI_DEVICE(dev);
 649
 650     isa_bus_new(DEVICE(d), get_system_memory(),
 651                 pci_address_space_io(dev));
 652
 653     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 654                           "piix3-reset-control", 1);
 655     memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
 656                                         &d->rcr_mem, 1);
 657
 658     qemu_register_reset(piix3_reset, d);
 659 }
 660
 661 static void pci_piix3_class_init(ObjectClass *klass, void *data)
 662 {
 663     DeviceClass *dc = DEVICE_CLASS(klass);
 664     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 665
 666     dc->desc        = "ISA bridge";
 667     dc->vmsd        = &vmstate_piix3;
 668     dc->hotpluggable   = false;
 669     k->realize      = piix3_realize;
 670     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 671     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 672     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 673     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 674     /*
 675      * Reason: part of PIIX3 southbridge, needs to be wired up by
 676      * pc_piix.c's pc_init1()
 677      */
 678     dc->cannot_instantiate_with_device_add_yet = true;
 679 }
 680
 681 static const TypeInfo piix3_pci_type_info = {
 682     .name = TYPE_PIIX3_PCI_DEVICE,
 683     .parent = TYPE_PCI_DEVICE,
 684     .instance_size = sizeof(PIIX3State),
 685     .abstract = true,
 686     .class_init = pci_piix3_class_init,
 687 };
 688
 689 static void piix3_class_init(ObjectClass *klass, void *data)
 690 {
 691     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 692
 693     k->config_write = piix3_write_config;
 694 }
 695
 696 static const TypeInfo piix3_info = {
 697     .name          = "PIIX3",
 698     .parent        = TYPE_PIIX3_PCI_DEVICE,
 699     .class_init    = piix3_class_init,
 700 };
 701
 702 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 703 {
 704     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 705
 706     k->config_write = piix3_write_config_xen;
 707 };
 708
 709 static const TypeInfo piix3_xen_info = {
 710     .name          = "PIIX3-xen",
 711     .parent        = TYPE_PIIX3_PCI_DEVICE,
 712     .class_init    = piix3_xen_class_init,
 713 };
 714
 715 static void i440fx_class_init(ObjectClass *klass, void *data)
 716 {
 717     DeviceClass *dc = DEVICE_CLASS(klass);
 718     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 719
 720     k->realize = i440fx_realize;
 721     k->config_write = i440fx_write_config;
 722     k->vendor_id = PCI_VENDOR_ID_INTEL;
 723     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 724     k->revision = 0x02;
 725     k->class_id = PCI_CLASS_BRIDGE_HOST;
 726     dc->desc = "Host bridge";
 727     dc->vmsd = &vmstate_i440fx;
 728     /*
 729      * PCI-facing part of the host bridge, not usable without the
 730      * host-facing part, which can't be device_add'ed, yet.
 731      */
 732     dc->cannot_instantiate_with_device_add_yet = true;
 733     dc->hotpluggable   = false;
 734 }
 735
 736 static const TypeInfo i440fx_info = {
 737     .name          = TYPE_I440FX_PCI_DEVICE,
 738     .parent        = TYPE_PCI_DEVICE,
 739     .instance_size = sizeof(PCII440FXState),
 740     .class_init    = i440fx_class_init,
 741 };
 742
 743 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 744                                                 PCIBus *rootbus)
 745 {
 746     I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
 747
 748     /* For backwards compat with old device paths */
 749     if (s->short_root_bus) {
 750         return "0000";
 751     }
 752     return "0000:00";
 753 }
 754
 755 static Property i440fx_props[] = {
 756     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
 757                      pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
 758     DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
 759     DEFINE_PROP_END_OF_LIST(),
 760 };
 761
 762 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 763 {
 764     DeviceClass *dc = DEVICE_CLASS(klass);
 765     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 766
 767     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 768     dc->realize = i440fx_pcihost_realize;
 769     dc->fw_name = "pci";
 770     dc->props = i440fx_props;
 771 }
 772
 773 static const TypeInfo i440fx_pcihost_info = {
 774     .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 775     .parent        = TYPE_PCI_HOST_BRIDGE,
 776     .instance_size = sizeof(I440FXState),
 777     .instance_init = i440fx_pcihost_initfn,
 778     .class_init    = i440fx_pcihost_class_init,
 779 };
 780
 781 static void i440fx_register_types(void)
 782 {
 783     type_register_static(&i440fx_info);
 784     type_register_static(&piix3_pci_type_info);
 785     type_register_static(&piix3_info);
 786     type_register_static(&piix3_xen_info);
 787     type_register_static(&i440fx_pcihost_info);
 788 }
 789
 790 type_init(i440fx_register_types)