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25 #include "qemu/osdep.h"
27 #include "hw/ssi/stm32f2xx_spi.h"
29 #ifndef STM_SPI_ERR_DEBUG
30 #define STM_SPI_ERR_DEBUG 0
33 #define DB_PRINT_L(lvl, fmt, args...) do { \
34 if (STM_SPI_ERR_DEBUG >= lvl) { \
35 qemu_log("%s: " fmt, __func__, ## args); \
39 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
41 static void stm32f2xx_spi_reset(DeviceState *dev)
43 STM32F2XXSPIState *s = STM32F2XX_SPI(dev);
45 s->spi_cr1 = 0x00000000;
46 s->spi_cr2 = 0x00000000;
47 s->spi_sr = 0x0000000A;
48 s->spi_dr = 0x0000000C;
49 s->spi_crcpr = 0x00000007;
50 s->spi_rxcrcr = 0x00000000;
51 s->spi_txcrcr = 0x00000000;
52 s->spi_i2scfgr = 0x00000000;
53 s->spi_i2spr = 0x00000002;
56 static void stm32f2xx_spi_transfer(STM32F2XXSPIState *s)
58 DB_PRINT("Data to send: 0x%x\n", s->spi_dr);
60 s->spi_dr = ssi_transfer(s->ssi, s->spi_dr);
61 s->spi_sr |= STM_SPI_SR_RXNE;
63 DB_PRINT("Data received: 0x%x\n", s->spi_dr);
66 static uint64_t stm32f2xx_spi_read(void *opaque, hwaddr addr,
69 STM32F2XXSPIState *s = opaque;
71 DB_PRINT("Address: 0x%" HWADDR_PRIx "\n", addr);
77 qemu_log_mask(LOG_UNIMP, "%s: Interrupts and DMA are not implemented\n",
83 stm32f2xx_spi_transfer(s);
84 s->spi_sr &= ~STM_SPI_SR_RXNE;
87 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
88 "are included for compatibility\n", __func__);
91 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
92 "are included for compatibility\n", __func__);
95 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented, the registers " \
96 "are included for compatibility\n", __func__);
99 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
100 "are included for compatibility\n", __func__);
101 return s->spi_i2scfgr;
103 qemu_log_mask(LOG_UNIMP, "%s: I2S is not implemented, the registers " \
104 "are included for compatibility\n", __func__);
107 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n",
114 static void stm32f2xx_spi_write(void *opaque, hwaddr addr,
115 uint64_t val64, unsigned int size)
117 STM32F2XXSPIState *s = opaque;
118 uint32_t value = val64;
120 DB_PRINT("Address: 0x%" HWADDR_PRIx ", Value: 0x%x\n", addr, value);
127 qemu_log_mask(LOG_UNIMP, "%s: " \
128 "Interrupts and DMA are not implemented\n", __func__);
132 /* Read only register, except for clearing the CRCERR bit, which
138 stm32f2xx_spi_transfer(s);
141 qemu_log_mask(LOG_UNIMP, "%s: CRC is not implemented\n", __func__);
144 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
145 "0x%" HWADDR_PRIx "\n", __func__, addr);
148 qemu_log_mask(LOG_GUEST_ERROR, "%s: Read only register: " \
149 "0x%" HWADDR_PRIx "\n", __func__, addr);
151 case STM_SPI_I2SCFGR:
152 qemu_log_mask(LOG_UNIMP, "%s: " \
153 "I2S is not implemented\n", __func__);
156 qemu_log_mask(LOG_UNIMP, "%s: " \
157 "I2S is not implemented\n", __func__);
160 qemu_log_mask(LOG_GUEST_ERROR,
161 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
165 static const MemoryRegionOps stm32f2xx_spi_ops = {
166 .read = stm32f2xx_spi_read,
167 .write = stm32f2xx_spi_write,
168 .endianness = DEVICE_NATIVE_ENDIAN,
171 static const VMStateDescription vmstate_stm32f2xx_spi = {
172 .name = TYPE_STM32F2XX_SPI,
174 .minimum_version_id = 1,
175 .fields = (VMStateField[]) {
176 VMSTATE_UINT32(spi_cr1, STM32F2XXSPIState),
177 VMSTATE_UINT32(spi_cr2, STM32F2XXSPIState),
178 VMSTATE_UINT32(spi_sr, STM32F2XXSPIState),
179 VMSTATE_UINT32(spi_dr, STM32F2XXSPIState),
180 VMSTATE_UINT32(spi_crcpr, STM32F2XXSPIState),
181 VMSTATE_UINT32(spi_rxcrcr, STM32F2XXSPIState),
182 VMSTATE_UINT32(spi_txcrcr, STM32F2XXSPIState),
183 VMSTATE_UINT32(spi_i2scfgr, STM32F2XXSPIState),
184 VMSTATE_UINT32(spi_i2spr, STM32F2XXSPIState),
185 VMSTATE_END_OF_LIST()
189 static void stm32f2xx_spi_init(Object *obj)
191 STM32F2XXSPIState *s = STM32F2XX_SPI(obj);
192 DeviceState *dev = DEVICE(obj);
194 memory_region_init_io(&s->mmio, obj, &stm32f2xx_spi_ops, s,
195 TYPE_STM32F2XX_SPI, 0x400);
196 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
198 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
200 s->ssi = ssi_create_bus(dev, "ssi");
203 static void stm32f2xx_spi_class_init(ObjectClass *klass, void *data)
205 DeviceClass *dc = DEVICE_CLASS(klass);
207 dc->reset = stm32f2xx_spi_reset;
208 dc->vmsd = &vmstate_stm32f2xx_spi;
211 static const TypeInfo stm32f2xx_spi_info = {
212 .name = TYPE_STM32F2XX_SPI,
213 .parent = TYPE_SYS_BUS_DEVICE,
214 .instance_size = sizeof(STM32F2XXSPIState),
215 .instance_init = stm32f2xx_spi_init,
216 .class_init = stm32f2xx_spi_class_init,
219 static void stm32f2xx_spi_register_types(void)
221 type_register_static(&stm32f2xx_spi_info);
224 type_init(stm32f2xx_spi_register_types)