hw/timer/milkymist-sysctl.c

   1 /*
   2  *  QEMU model of the Milkymist System Controller.
   3  *
   4  *  Copyright (c) 2010-2012 Michael Walle <[email protected]>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/sysctl.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/irq.h"
  26 #include "hw/sysbus.h"
  27 #include "migration/vmstate.h"
  28 #include "sysemu/sysemu.h"
  29 #include "trace.h"
  30 #include "qemu/timer.h"
  31 #include "hw/ptimer.h"
  32 #include "qemu/error-report.h"
  33 #include "qemu/main-loop.h"
  34 #include "qemu/module.h"
  35
  36 enum {
  37     CTRL_ENABLE      = (1<<0),
  38     CTRL_AUTORESTART = (1<<1),
  39 };
  40
  41 enum {
  42     ICAP_READY       = (1<<0),
  43 };
  44
  45 enum {
  46     R_GPIO_IN         = 0,
  47     R_GPIO_OUT,
  48     R_GPIO_INTEN,
  49     R_TIMER0_CONTROL  = 4,
  50     R_TIMER0_COMPARE,
  51     R_TIMER0_COUNTER,
  52     R_TIMER1_CONTROL  = 8,
  53     R_TIMER1_COMPARE,
  54     R_TIMER1_COUNTER,
  55     R_ICAP = 16,
  56     R_DBG_SCRATCHPAD  = 20,
  57     R_DBG_WRITE_LOCK,
  58     R_CLK_FREQUENCY   = 29,
  59     R_CAPABILITIES,
  60     R_SYSTEM_ID,
  61     R_MAX
  62 };
  63
  64 #define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
  65 #define MILKYMIST_SYSCTL(obj) \
  66     OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)
  67
  68 struct MilkymistSysctlState {
  69     SysBusDevice parent_obj;
  70
  71     MemoryRegion regs_region;
  72
  73     QEMUBH *bh0;
  74     QEMUBH *bh1;
  75     ptimer_state *ptimer0;
  76     ptimer_state *ptimer1;
  77
  78     uint32_t freq_hz;
  79     uint32_t capabilities;
  80     uint32_t systemid;
  81     uint32_t strappings;
  82
  83     uint32_t regs[R_MAX];
  84
  85     qemu_irq gpio_irq;
  86     qemu_irq timer0_irq;
  87     qemu_irq timer1_irq;
  88 };
  89 typedef struct MilkymistSysctlState MilkymistSysctlState;
  90
  91 static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
  92 {
  93     trace_milkymist_sysctl_icap_write(value);
  94     switch (value & 0xffff) {
  95     case 0x000e:
  96         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  97         break;
  98     }
  99 }
 100
 101 static uint64_t sysctl_read(void *opaque, hwaddr addr,
 102                             unsigned size)
 103 {
 104     MilkymistSysctlState *s = opaque;
 105     uint32_t r = 0;
 106
 107     addr >>= 2;
 108     switch (addr) {
 109     case R_TIMER0_COUNTER:
 110         r = (uint32_t)ptimer_get_count(s->ptimer0);
 111         /* milkymist timer counts up */
 112         r = s->regs[R_TIMER0_COMPARE] - r;
 113         break;
 114     case R_TIMER1_COUNTER:
 115         r = (uint32_t)ptimer_get_count(s->ptimer1);
 116         /* milkymist timer counts up */
 117         r = s->regs[R_TIMER1_COMPARE] - r;
 118         break;
 119     case R_GPIO_IN:
 120     case R_GPIO_OUT:
 121     case R_GPIO_INTEN:
 122     case R_TIMER0_CONTROL:
 123     case R_TIMER0_COMPARE:
 124     case R_TIMER1_CONTROL:
 125     case R_TIMER1_COMPARE:
 126     case R_ICAP:
 127     case R_DBG_SCRATCHPAD:
 128     case R_DBG_WRITE_LOCK:
 129     case R_CLK_FREQUENCY:
 130     case R_CAPABILITIES:
 131     case R_SYSTEM_ID:
 132         r = s->regs[addr];
 133         break;
 134
 135     default:
 136         error_report("milkymist_sysctl: read access to unknown register 0x"
 137                 TARGET_FMT_plx, addr << 2);
 138         break;
 139     }
 140
 141     trace_milkymist_sysctl_memory_read(addr << 2, r);
 142
 143     return r;
 144 }
 145
 146 static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
 147                          unsigned size)
 148 {
 149     MilkymistSysctlState *s = opaque;
 150
 151     trace_milkymist_sysctl_memory_write(addr, value);
 152
 153     addr >>= 2;
 154     switch (addr) {
 155     case R_GPIO_OUT:
 156     case R_GPIO_INTEN:
 157     case R_TIMER0_COUNTER:
 158     case R_TIMER1_COUNTER:
 159     case R_DBG_SCRATCHPAD:
 160         s->regs[addr] = value;
 161         break;
 162     case R_TIMER0_COMPARE:
 163         ptimer_set_limit(s->ptimer0, value, 0);
 164         s->regs[addr] = value;
 165         break;
 166     case R_TIMER1_COMPARE:
 167         ptimer_set_limit(s->ptimer1, value, 0);
 168         s->regs[addr] = value;
 169         break;
 170     case R_TIMER0_CONTROL:
 171         s->regs[addr] = value;
 172         if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
 173             trace_milkymist_sysctl_start_timer0();
 174             ptimer_set_count(s->ptimer0,
 175                     s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
 176             ptimer_run(s->ptimer0, 0);
 177         } else {
 178             trace_milkymist_sysctl_stop_timer0();
 179             ptimer_stop(s->ptimer0);
 180         }
 181         break;
 182     case R_TIMER1_CONTROL:
 183         s->regs[addr] = value;
 184         if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
 185             trace_milkymist_sysctl_start_timer1();
 186             ptimer_set_count(s->ptimer1,
 187                     s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
 188             ptimer_run(s->ptimer1, 0);
 189         } else {
 190             trace_milkymist_sysctl_stop_timer1();
 191             ptimer_stop(s->ptimer1);
 192         }
 193         break;
 194     case R_ICAP:
 195         sysctl_icap_write(s, value);
 196         break;
 197     case R_DBG_WRITE_LOCK:
 198         s->regs[addr] = 1;
 199         break;
 200     case R_SYSTEM_ID:
 201         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 202         break;
 203
 204     case R_GPIO_IN:
 205     case R_CLK_FREQUENCY:
 206     case R_CAPABILITIES:
 207         error_report("milkymist_sysctl: write to read-only register 0x"
 208                 TARGET_FMT_plx, addr << 2);
 209         break;
 210
 211     default:
 212         error_report("milkymist_sysctl: write access to unknown register 0x"
 213                 TARGET_FMT_plx, addr << 2);
 214         break;
 215     }
 216 }
 217
 218 static const MemoryRegionOps sysctl_mmio_ops = {
 219     .read = sysctl_read,
 220     .write = sysctl_write,
 221     .valid = {
 222         .min_access_size = 4,
 223         .max_access_size = 4,
 224     },
 225     .endianness = DEVICE_NATIVE_ENDIAN,
 226 };
 227
 228 static void timer0_hit(void *opaque)
 229 {
 230     MilkymistSysctlState *s = opaque;
 231
 232     if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
 233         s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
 234         trace_milkymist_sysctl_stop_timer0();
 235         ptimer_stop(s->ptimer0);
 236     }
 237
 238     trace_milkymist_sysctl_pulse_irq_timer0();
 239     qemu_irq_pulse(s->timer0_irq);
 240 }
 241
 242 static void timer1_hit(void *opaque)
 243 {
 244     MilkymistSysctlState *s = opaque;
 245
 246     if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
 247         s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
 248         trace_milkymist_sysctl_stop_timer1();
 249         ptimer_stop(s->ptimer1);
 250     }
 251
 252     trace_milkymist_sysctl_pulse_irq_timer1();
 253     qemu_irq_pulse(s->timer1_irq);
 254 }
 255
 256 static void milkymist_sysctl_reset(DeviceState *d)
 257 {
 258     MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
 259     int i;
 260
 261     for (i = 0; i < R_MAX; i++) {
 262         s->regs[i] = 0;
 263     }
 264
 265     ptimer_stop(s->ptimer0);
 266     ptimer_stop(s->ptimer1);
 267
 268     /* defaults */
 269     s->regs[R_ICAP] = ICAP_READY;
 270     s->regs[R_SYSTEM_ID] = s->systemid;
 271     s->regs[R_CLK_FREQUENCY] = s->freq_hz;
 272     s->regs[R_CAPABILITIES] = s->capabilities;
 273     s->regs[R_GPIO_IN] = s->strappings;
 274 }
 275
 276 static void milkymist_sysctl_init(Object *obj)
 277 {
 278     MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
 279     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 280
 281     sysbus_init_irq(dev, &s->gpio_irq);
 282     sysbus_init_irq(dev, &s->timer0_irq);
 283     sysbus_init_irq(dev, &s->timer1_irq);
 284
 285     s->bh0 = qemu_bh_new(timer0_hit, s);
 286     s->bh1 = qemu_bh_new(timer1_hit, s);
 287     s->ptimer0 = ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT);
 288     s->ptimer1 = ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT);
 289
 290     memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
 291             "milkymist-sysctl", R_MAX * 4);
 292     sysbus_init_mmio(dev, &s->regs_region);
 293 }
 294
 295 static void milkymist_sysctl_realize(DeviceState *dev, Error **errp)
 296 {
 297     MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);
 298
 299     ptimer_set_freq(s->ptimer0, s->freq_hz);
 300     ptimer_set_freq(s->ptimer1, s->freq_hz);
 301 }
 302
 303 static const VMStateDescription vmstate_milkymist_sysctl = {
 304     .name = "milkymist-sysctl",
 305     .version_id = 1,
 306     .minimum_version_id = 1,
 307     .fields = (VMStateField[]) {
 308         VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
 309         VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
 310         VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
 311         VMSTATE_END_OF_LIST()
 312     }
 313 };
 314
 315 static Property milkymist_sysctl_properties[] = {
 316     DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
 317     freq_hz, 80000000),
 318     DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
 319     capabilities, 0x00000000),
 320     DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
 321     systemid, 0x10014d31),
 322     DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
 323     strappings, 0x00000001),
 324     DEFINE_PROP_END_OF_LIST(),
 325 };
 326
 327 static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
 328 {
 329     DeviceClass *dc = DEVICE_CLASS(klass);
 330
 331     dc->realize = milkymist_sysctl_realize;
 332     dc->reset = milkymist_sysctl_reset;
 333     dc->vmsd = &vmstate_milkymist_sysctl;
 334     dc->props = milkymist_sysctl_properties;
 335 }
 336
 337 static const TypeInfo milkymist_sysctl_info = {
 338     .name          = TYPE_MILKYMIST_SYSCTL,
 339     .parent        = TYPE_SYS_BUS_DEVICE,
 340     .instance_size = sizeof(MilkymistSysctlState),
 341     .instance_init = milkymist_sysctl_init,
 342     .class_init    = milkymist_sysctl_class_init,
 343 };
 344
 345 static void milkymist_sysctl_register_types(void)
 346 {
 347     type_register_static(&milkymist_sysctl_info);
 348 }
 349
 350 type_init(milkymist_sysctl_register_types)