hw/timer/exynos4210_rtc.c

   1 /*
   2  * Samsung exynos4210 Real Time Clock
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *  Ogurtsov Oleg <[email protected]>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License as published by the
   9  *  Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  */
  21
  22 /* Description:
  23  * Register RTCCON:
  24  *  CLKSEL Bit[1] not used
  25  *  CLKOUTEN Bit[9] not used
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qemu-common.h"
  30 #include "qemu/log.h"
  31 #include "qemu/main-loop.h"
  32 #include "qemu/module.h"
  33 #include "hw/sysbus.h"
  34 #include "migration/vmstate.h"
  35 #include "qemu/timer.h"
  36 #include "qemu/bcd.h"
  37 #include "hw/ptimer.h"
  38
  39 #include "hw/irq.h"
  40 #include "sysemu/sysemu.h"
  41
  42 #include "hw/arm/exynos4210.h"
  43
  44 #define DEBUG_RTC 0
  45
  46 #if DEBUG_RTC
  47 #define DPRINTF(fmt, ...) \
  48         do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \
  49                 ## __VA_ARGS__); } while (0)
  50 #else
  51 #define DPRINTF(fmt, ...) do {} while (0)
  52 #endif
  53
  54 #define     EXYNOS4210_RTC_REG_MEM_SIZE     0x0100
  55
  56 #define     INTP            0x0030
  57 #define     RTCCON          0x0040
  58 #define     TICCNT          0x0044
  59 #define     RTCALM          0x0050
  60 #define     ALMSEC          0x0054
  61 #define     ALMMIN          0x0058
  62 #define     ALMHOUR         0x005C
  63 #define     ALMDAY          0x0060
  64 #define     ALMMON          0x0064
  65 #define     ALMYEAR         0x0068
  66 #define     BCDSEC          0x0070
  67 #define     BCDMIN          0x0074
  68 #define     BCDHOUR         0x0078
  69 #define     BCDDAY          0x007C
  70 #define     BCDDAYWEEK      0x0080
  71 #define     BCDMON          0x0084
  72 #define     BCDYEAR         0x0088
  73 #define     CURTICNT        0x0090
  74
  75 #define     TICK_TIMER_ENABLE   0x0100
  76 #define     TICNT_THRESHOLD     2
  77
  78
  79 #define     RTC_ENABLE          0x0001
  80
  81 #define     INTP_TICK_ENABLE    0x0001
  82 #define     INTP_ALM_ENABLE     0x0002
  83
  84 #define     ALARM_INT_ENABLE    0x0040
  85
  86 #define     RTC_BASE_FREQ       32768
  87
  88 #define TYPE_EXYNOS4210_RTC "exynos4210.rtc"
  89 #define EXYNOS4210_RTC(obj) \
  90     OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC)
  91
  92 typedef struct Exynos4210RTCState {
  93     SysBusDevice parent_obj;
  94
  95     MemoryRegion iomem;
  96
  97     /* registers */
  98     uint32_t    reg_intp;
  99     uint32_t    reg_rtccon;
 100     uint32_t    reg_ticcnt;
 101     uint32_t    reg_rtcalm;
 102     uint32_t    reg_almsec;
 103     uint32_t    reg_almmin;
 104     uint32_t    reg_almhour;
 105     uint32_t    reg_almday;
 106     uint32_t    reg_almmon;
 107     uint32_t    reg_almyear;
 108     uint32_t    reg_curticcnt;
 109
 110     ptimer_state    *ptimer;        /* tick timer */
 111     ptimer_state    *ptimer_1Hz;    /* clock timer */
 112     uint32_t        freq;
 113
 114     qemu_irq        tick_irq;   /* Time Tick Generator irq */
 115     qemu_irq        alm_irq;    /* alarm irq */
 116
 117     struct tm   current_tm;     /* current time */
 118 } Exynos4210RTCState;
 119
 120 #define TICCKSEL(value) ((value & (0x0F << 4)) >> 4)
 121
 122 /*** VMState ***/
 123 static const VMStateDescription vmstate_exynos4210_rtc_state = {
 124     .name = "exynos4210.rtc",
 125     .version_id = 1,
 126     .minimum_version_id = 1,
 127     .fields = (VMStateField[]) {
 128         VMSTATE_UINT32(reg_intp, Exynos4210RTCState),
 129         VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState),
 130         VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState),
 131         VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState),
 132         VMSTATE_UINT32(reg_almsec, Exynos4210RTCState),
 133         VMSTATE_UINT32(reg_almmin, Exynos4210RTCState),
 134         VMSTATE_UINT32(reg_almhour, Exynos4210RTCState),
 135         VMSTATE_UINT32(reg_almday, Exynos4210RTCState),
 136         VMSTATE_UINT32(reg_almmon, Exynos4210RTCState),
 137         VMSTATE_UINT32(reg_almyear, Exynos4210RTCState),
 138         VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState),
 139         VMSTATE_PTIMER(ptimer, Exynos4210RTCState),
 140         VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState),
 141         VMSTATE_UINT32(freq, Exynos4210RTCState),
 142         VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState),
 143         VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState),
 144         VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState),
 145         VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState),
 146         VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState),
 147         VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState),
 148         VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState),
 149         VMSTATE_END_OF_LIST()
 150     }
 151 };
 152
 153 #define BCD3DIGITS(x) \
 154     ((uint32_t)to_bcd((uint8_t)(x % 100)) + \
 155     ((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8))
 156
 157 static void check_alarm_raise(Exynos4210RTCState *s)
 158 {
 159     unsigned int alarm_raise = 0;
 160     struct tm stm = s->current_tm;
 161
 162     if ((s->reg_rtcalm & 0x01) &&
 163         (to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) {
 164         alarm_raise = 1;
 165     }
 166     if ((s->reg_rtcalm & 0x02) &&
 167         (to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) {
 168         alarm_raise = 1;
 169     }
 170     if ((s->reg_rtcalm & 0x04) &&
 171         (to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) {
 172         alarm_raise = 1;
 173     }
 174     if ((s->reg_rtcalm & 0x08) &&
 175         (to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) {
 176         alarm_raise = 1;
 177     }
 178     if ((s->reg_rtcalm & 0x10) &&
 179          (to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) {
 180         alarm_raise = 1;
 181     }
 182     if ((s->reg_rtcalm & 0x20) &&
 183         (BCD3DIGITS(stm.tm_year) == s->reg_almyear)) {
 184         alarm_raise = 1;
 185     }
 186
 187     if (alarm_raise) {
 188         DPRINTF("ALARM IRQ\n");
 189         /* set irq status */
 190         s->reg_intp |= INTP_ALM_ENABLE;
 191         qemu_irq_raise(s->alm_irq);
 192     }
 193 }
 194
 195 /*
 196  * RTC update frequency
 197  * Parameters:
 198  *     reg_value - current RTCCON register or his new value
 199  */
 200 static void exynos4210_rtc_update_freq(Exynos4210RTCState *s,
 201                                        uint32_t reg_value)
 202 {
 203     uint32_t freq;
 204
 205     freq = s->freq;
 206     /* set frequncy for time generator */
 207     s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));
 208
 209     if (freq != s->freq) {
 210         ptimer_set_freq(s->ptimer, s->freq);
 211         DPRINTF("freq=%dHz\n", s->freq);
 212     }
 213 }
 214
 215 /* month is between 0 and 11. */
 216 static int get_days_in_month(int month, int year)
 217 {
 218     static const int days_tab[12] = {
 219         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 220     };
 221     int d;
 222     if ((unsigned)month >= 12) {
 223         return 31;
 224     }
 225     d = days_tab[month];
 226     if (month == 1) {
 227         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) {
 228             d++;
 229         }
 230     }
 231     return d;
 232 }
 233
 234 /* update 'tm' to the next second */
 235 static void rtc_next_second(struct tm *tm)
 236 {
 237     int days_in_month;
 238
 239     tm->tm_sec++;
 240     if ((unsigned)tm->tm_sec >= 60) {
 241         tm->tm_sec = 0;
 242         tm->tm_min++;
 243         if ((unsigned)tm->tm_min >= 60) {
 244             tm->tm_min = 0;
 245             tm->tm_hour++;
 246             if ((unsigned)tm->tm_hour >= 24) {
 247                 tm->tm_hour = 0;
 248                 /* next day */
 249                 tm->tm_wday++;
 250                 if ((unsigned)tm->tm_wday >= 7) {
 251                     tm->tm_wday = 0;
 252                 }
 253                 days_in_month = get_days_in_month(tm->tm_mon,
 254                                                   tm->tm_year + 1900);
 255                 tm->tm_mday++;
 256                 if (tm->tm_mday < 1) {
 257                     tm->tm_mday = 1;
 258                 } else if (tm->tm_mday > days_in_month) {
 259                     tm->tm_mday = 1;
 260                     tm->tm_mon++;
 261                     if (tm->tm_mon >= 12) {
 262                         tm->tm_mon = 0;
 263                         tm->tm_year++;
 264                     }
 265                 }
 266             }
 267         }
 268     }
 269 }
 270
 271 /*
 272  * tick handler
 273  */
 274 static void exynos4210_rtc_tick(void *opaque)
 275 {
 276     Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
 277
 278     DPRINTF("TICK IRQ\n");
 279     /* set irq status */
 280     s->reg_intp |= INTP_TICK_ENABLE;
 281     /* raise IRQ */
 282     qemu_irq_raise(s->tick_irq);
 283
 284     /* restart timer */
 285     ptimer_set_count(s->ptimer, s->reg_ticcnt);
 286     ptimer_run(s->ptimer, 1);
 287 }
 288
 289 /*
 290  * 1Hz clock handler
 291  */
 292 static void exynos4210_rtc_1Hz_tick(void *opaque)
 293 {
 294     Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
 295
 296     rtc_next_second(&s->current_tm);
 297     /* DPRINTF("1Hz tick\n"); */
 298
 299     /* raise IRQ */
 300     if (s->reg_rtcalm & ALARM_INT_ENABLE) {
 301         check_alarm_raise(s);
 302     }
 303
 304     ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
 305     ptimer_run(s->ptimer_1Hz, 1);
 306 }
 307
 308 /*
 309  * RTC Read
 310  */
 311 static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
 312         unsigned size)
 313 {
 314     uint32_t value = 0;
 315     Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
 316
 317     switch (offset) {
 318     case INTP:
 319         value = s->reg_intp;
 320         break;
 321     case RTCCON:
 322         value = s->reg_rtccon;
 323         break;
 324     case TICCNT:
 325         value = s->reg_ticcnt;
 326         break;
 327     case RTCALM:
 328         value = s->reg_rtcalm;
 329         break;
 330     case ALMSEC:
 331         value = s->reg_almsec;
 332         break;
 333     case ALMMIN:
 334         value = s->reg_almmin;
 335         break;
 336     case ALMHOUR:
 337         value = s->reg_almhour;
 338         break;
 339     case ALMDAY:
 340         value = s->reg_almday;
 341         break;
 342     case ALMMON:
 343         value = s->reg_almmon;
 344         break;
 345     case ALMYEAR:
 346         value = s->reg_almyear;
 347         break;
 348
 349     case BCDSEC:
 350         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec);
 351         break;
 352     case BCDMIN:
 353         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min);
 354         break;
 355     case BCDHOUR:
 356         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour);
 357         break;
 358     case BCDDAYWEEK:
 359         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday);
 360         break;
 361     case BCDDAY:
 362         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday);
 363         break;
 364     case BCDMON:
 365         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1);
 366         break;
 367     case BCDYEAR:
 368         value = BCD3DIGITS(s->current_tm.tm_year);
 369         break;
 370
 371     case CURTICNT:
 372         s->reg_curticcnt = ptimer_get_count(s->ptimer);
 373         value = s->reg_curticcnt;
 374         break;
 375
 376     default:
 377         qemu_log_mask(LOG_GUEST_ERROR,
 378                       "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
 379                       offset);
 380         break;
 381     }
 382     return value;
 383 }
 384
 385 /*
 386  * RTC Write
 387  */
 388 static void exynos4210_rtc_write(void *opaque, hwaddr offset,
 389         uint64_t value, unsigned size)
 390 {
 391     Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
 392
 393     switch (offset) {
 394     case INTP:
 395         if (value & INTP_ALM_ENABLE) {
 396             qemu_irq_lower(s->alm_irq);
 397             s->reg_intp &= (~INTP_ALM_ENABLE);
 398         }
 399         if (value & INTP_TICK_ENABLE) {
 400             qemu_irq_lower(s->tick_irq);
 401             s->reg_intp &= (~INTP_TICK_ENABLE);
 402         }
 403         break;
 404     case RTCCON:
 405         if (value & RTC_ENABLE) {
 406             exynos4210_rtc_update_freq(s, value);
 407         }
 408         if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) {
 409             /* clock timer */
 410             ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
 411             ptimer_run(s->ptimer_1Hz, 1);
 412             DPRINTF("run clock timer\n");
 413         }
 414         if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) {
 415             /* tick timer */
 416             ptimer_stop(s->ptimer);
 417             /* clock timer */
 418             ptimer_stop(s->ptimer_1Hz);
 419             DPRINTF("stop all timers\n");
 420         }
 421         if (value & RTC_ENABLE) {
 422             if ((value & TICK_TIMER_ENABLE) >
 423                 (s->reg_rtccon & TICK_TIMER_ENABLE) &&
 424                 (s->reg_ticcnt)) {
 425                 ptimer_set_count(s->ptimer, s->reg_ticcnt);
 426                 ptimer_run(s->ptimer, 1);
 427                 DPRINTF("run tick timer\n");
 428             }
 429             if ((value & TICK_TIMER_ENABLE) <
 430                 (s->reg_rtccon & TICK_TIMER_ENABLE)) {
 431                 ptimer_stop(s->ptimer);
 432             }
 433         }
 434         s->reg_rtccon = value;
 435         break;
 436     case TICCNT:
 437         if (value > TICNT_THRESHOLD) {
 438             s->reg_ticcnt = value;
 439         } else {
 440             qemu_log_mask(LOG_GUEST_ERROR,
 441                           "exynos4210.rtc: bad TICNT value %u",
 442                           (uint32_t)value);
 443         }
 444         break;
 445
 446     case RTCALM:
 447         s->reg_rtcalm = value;
 448         break;
 449     case ALMSEC:
 450         s->reg_almsec = (value & 0x7f);
 451         break;
 452     case ALMMIN:
 453         s->reg_almmin = (value & 0x7f);
 454         break;
 455     case ALMHOUR:
 456         s->reg_almhour = (value & 0x3f);
 457         break;
 458     case ALMDAY:
 459         s->reg_almday = (value & 0x3f);
 460         break;
 461     case ALMMON:
 462         s->reg_almmon = (value & 0x1f);
 463         break;
 464     case ALMYEAR:
 465         s->reg_almyear = (value & 0x0fff);
 466         break;
 467
 468     case BCDSEC:
 469         if (s->reg_rtccon & RTC_ENABLE) {
 470             s->current_tm.tm_sec = (int)from_bcd((uint8_t)value);
 471         }
 472         break;
 473     case BCDMIN:
 474         if (s->reg_rtccon & RTC_ENABLE) {
 475             s->current_tm.tm_min = (int)from_bcd((uint8_t)value);
 476         }
 477         break;
 478     case BCDHOUR:
 479         if (s->reg_rtccon & RTC_ENABLE) {
 480             s->current_tm.tm_hour = (int)from_bcd((uint8_t)value);
 481         }
 482         break;
 483     case BCDDAYWEEK:
 484         if (s->reg_rtccon & RTC_ENABLE) {
 485             s->current_tm.tm_wday = (int)from_bcd((uint8_t)value);
 486         }
 487         break;
 488     case BCDDAY:
 489         if (s->reg_rtccon & RTC_ENABLE) {
 490             s->current_tm.tm_mday = (int)from_bcd((uint8_t)value);
 491         }
 492         break;
 493     case BCDMON:
 494         if (s->reg_rtccon & RTC_ENABLE) {
 495             s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1;
 496         }
 497         break;
 498     case BCDYEAR:
 499         if (s->reg_rtccon & RTC_ENABLE) {
 500             /* 3 digits */
 501             s->current_tm.tm_year = (int)from_bcd((uint8_t)value) +
 502                     (int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100;
 503         }
 504         break;
 505
 506     default:
 507         qemu_log_mask(LOG_GUEST_ERROR,
 508                       "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
 509                       offset);
 510         break;
 511
 512     }
 513 }
 514
 515 /*
 516  * Set default values to timer fields and registers
 517  */
 518 static void exynos4210_rtc_reset(DeviceState *d)
 519 {
 520     Exynos4210RTCState *s = EXYNOS4210_RTC(d);
 521
 522     qemu_get_timedate(&s->current_tm, 0);
 523
 524     DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
 525             s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday,
 526             s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec);
 527
 528     s->reg_intp = 0;
 529     s->reg_rtccon = 0;
 530     s->reg_ticcnt = 0;
 531     s->reg_rtcalm = 0;
 532     s->reg_almsec = 0;
 533     s->reg_almmin = 0;
 534     s->reg_almhour = 0;
 535     s->reg_almday = 0;
 536     s->reg_almmon = 0;
 537     s->reg_almyear = 0;
 538
 539     s->reg_curticcnt = 0;
 540
 541     exynos4210_rtc_update_freq(s, s->reg_rtccon);
 542     ptimer_stop(s->ptimer);
 543     ptimer_stop(s->ptimer_1Hz);
 544 }
 545
 546 static const MemoryRegionOps exynos4210_rtc_ops = {
 547     .read = exynos4210_rtc_read,
 548     .write = exynos4210_rtc_write,
 549     .endianness = DEVICE_NATIVE_ENDIAN,
 550 };
 551
 552 /*
 553  * RTC timer initialization
 554  */
 555 static void exynos4210_rtc_init(Object *obj)
 556 {
 557     Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
 558     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 559     QEMUBH *bh;
 560
 561     bh = qemu_bh_new(exynos4210_rtc_tick, s);
 562     s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
 563     ptimer_set_freq(s->ptimer, RTC_BASE_FREQ);
 564     exynos4210_rtc_update_freq(s, 0);
 565
 566     bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s);
 567     s->ptimer_1Hz = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
 568     ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ);
 569
 570     sysbus_init_irq(dev, &s->alm_irq);
 571     sysbus_init_irq(dev, &s->tick_irq);
 572
 573     memory_region_init_io(&s->iomem, obj, &exynos4210_rtc_ops, s,
 574                           "exynos4210-rtc", EXYNOS4210_RTC_REG_MEM_SIZE);
 575     sysbus_init_mmio(dev, &s->iomem);
 576 }
 577
 578 static void exynos4210_rtc_class_init(ObjectClass *klass, void *data)
 579 {
 580     DeviceClass *dc = DEVICE_CLASS(klass);
 581
 582     dc->reset = exynos4210_rtc_reset;
 583     dc->vmsd = &vmstate_exynos4210_rtc_state;
 584 }
 585
 586 static const TypeInfo exynos4210_rtc_info = {
 587     .name          = TYPE_EXYNOS4210_RTC,
 588     .parent        = TYPE_SYS_BUS_DEVICE,
 589     .instance_size = sizeof(Exynos4210RTCState),
 590     .instance_init = exynos4210_rtc_init,
 591     .class_init    = exynos4210_rtc_class_init,
 592 };
 593
 594 static void exynos4210_rtc_register_types(void)
 595 {
 596     type_register_static(&exynos4210_rtc_info);
 597 }
 598
 599 type_init(exynos4210_rtc_register_types)