target/i386/machine.c

   1 #include "qemu/osdep.h"
   2 #include "qemu-common.h"
   3 #include "cpu.h"
   4 #include "exec/exec-all.h"
   5 #include "hw/hw.h"
   6 #include "hw/boards.h"
   7 #include "hw/i386/pc.h"
   8 #include "hw/isa/isa.h"
   9 #include "migration/cpu.h"
  10
  11 #include "sysemu/kvm.h"
  12
  13 #include "qemu/error-report.h"
  14
  15 static const VMStateDescription vmstate_segment = {
  16     .name = "segment",
  17     .version_id = 1,
  18     .minimum_version_id = 1,
  19     .fields = (VMStateField[]) {
  20         VMSTATE_UINT32(selector, SegmentCache),
  21         VMSTATE_UINTTL(base, SegmentCache),
  22         VMSTATE_UINT32(limit, SegmentCache),
  23         VMSTATE_UINT32(flags, SegmentCache),
  24         VMSTATE_END_OF_LIST()
  25     }
  26 };
  27
  28 #define VMSTATE_SEGMENT(_field, _state) {                            \
  29     .name       = (stringify(_field)),                               \
  30     .size       = sizeof(SegmentCache),                              \
  31     .vmsd       = &vmstate_segment,                                  \
  32     .flags      = VMS_STRUCT,                                        \
  33     .offset     = offsetof(_state, _field)                           \
  34             + type_check(SegmentCache,typeof_field(_state, _field))  \
  35 }
  36
  37 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
  38     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
  39
  40 static const VMStateDescription vmstate_xmm_reg = {
  41     .name = "xmm_reg",
  42     .version_id = 1,
  43     .minimum_version_id = 1,
  44     .fields = (VMStateField[]) {
  45         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  46         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  47         VMSTATE_END_OF_LIST()
  48     }
  49 };
  50
  51 #define VMSTATE_XMM_REGS(_field, _state, _start)                         \
  52     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  53                              vmstate_xmm_reg, ZMMReg)
  54
  55 /* YMMH format is the same as XMM, but for bits 128-255 */
  56 static const VMStateDescription vmstate_ymmh_reg = {
  57     .name = "ymmh_reg",
  58     .version_id = 1,
  59     .minimum_version_id = 1,
  60     .fields = (VMStateField[]) {
  61         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  62         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  63         VMSTATE_END_OF_LIST()
  64     }
  65 };
  66
  67 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v)               \
  68     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v,    \
  69                              vmstate_ymmh_reg, ZMMReg)
  70
  71 static const VMStateDescription vmstate_zmmh_reg = {
  72     .name = "zmmh_reg",
  73     .version_id = 1,
  74     .minimum_version_id = 1,
  75     .fields = (VMStateField[]) {
  76         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  77         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
  78         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
  79         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
  80         VMSTATE_END_OF_LIST()
  81     }
  82 };
  83
  84 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start)                   \
  85     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  86                              vmstate_zmmh_reg, ZMMReg)
  87
  88 #ifdef TARGET_X86_64
  89 static const VMStateDescription vmstate_hi16_zmm_reg = {
  90     .name = "hi16_zmm_reg",
  91     .version_id = 1,
  92     .minimum_version_id = 1,
  93     .fields = (VMStateField[]) {
  94         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  95         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  96         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  97         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  98         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  99         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
 100         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
 101         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
 102         VMSTATE_END_OF_LIST()
 103     }
 104 };
 105
 106 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start)               \
 107     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
 108                              vmstate_hi16_zmm_reg, ZMMReg)
 109 #endif
 110
 111 static const VMStateDescription vmstate_bnd_regs = {
 112     .name = "bnd_regs",
 113     .version_id = 1,
 114     .minimum_version_id = 1,
 115     .fields = (VMStateField[]) {
 116         VMSTATE_UINT64(lb, BNDReg),
 117         VMSTATE_UINT64(ub, BNDReg),
 118         VMSTATE_END_OF_LIST()
 119     }
 120 };
 121
 122 #define VMSTATE_BND_REGS(_field, _state, _n)          \
 123     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
 124
 125 static const VMStateDescription vmstate_mtrr_var = {
 126     .name = "mtrr_var",
 127     .version_id = 1,
 128     .minimum_version_id = 1,
 129     .fields = (VMStateField[]) {
 130         VMSTATE_UINT64(base, MTRRVar),
 131         VMSTATE_UINT64(mask, MTRRVar),
 132         VMSTATE_END_OF_LIST()
 133     }
 134 };
 135
 136 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
 137     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
 138
 139 typedef struct x86_FPReg_tmp {
 140     FPReg *parent;
 141     uint64_t tmp_mant;
 142     uint16_t tmp_exp;
 143 } x86_FPReg_tmp;
 144
 145 static void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f)
 146 {
 147     CPU_LDoubleU temp;
 148
 149     temp.d = f;
 150     *pmant = temp.l.lower;
 151     *pexp = temp.l.upper;
 152 }
 153
 154 static floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper)
 155 {
 156     CPU_LDoubleU temp;
 157
 158     temp.l.upper = upper;
 159     temp.l.lower = mant;
 160     return temp.d;
 161 }
 162
 163 static void fpreg_pre_save(void *opaque)
 164 {
 165     x86_FPReg_tmp *tmp = opaque;
 166
 167     /* we save the real CPU data (in case of MMX usage only 'mant'
 168        contains the MMX register */
 169     cpu_get_fp80(&tmp->tmp_mant, &tmp->tmp_exp, tmp->parent->d);
 170 }
 171
 172 static int fpreg_post_load(void *opaque, int version)
 173 {
 174     x86_FPReg_tmp *tmp = opaque;
 175
 176     tmp->parent->d = cpu_set_fp80(tmp->tmp_mant, tmp->tmp_exp);
 177     return 0;
 178 }
 179
 180 static const VMStateDescription vmstate_fpreg_tmp = {
 181     .name = "fpreg_tmp",
 182     .post_load = fpreg_post_load,
 183     .pre_save  = fpreg_pre_save,
 184     .fields = (VMStateField[]) {
 185         VMSTATE_UINT64(tmp_mant, x86_FPReg_tmp),
 186         VMSTATE_UINT16(tmp_exp, x86_FPReg_tmp),
 187         VMSTATE_END_OF_LIST()
 188     }
 189 };
 190
 191 static const VMStateDescription vmstate_fpreg = {
 192     .name = "fpreg",
 193     .fields = (VMStateField[]) {
 194         VMSTATE_WITH_TMP(FPReg, x86_FPReg_tmp, vmstate_fpreg_tmp),
 195         VMSTATE_END_OF_LIST()
 196     }
 197 };
 198
 199 static void cpu_pre_save(void *opaque)
 200 {
 201     X86CPU *cpu = opaque;
 202     CPUX86State *env = &cpu->env;
 203     int i;
 204
 205     /* FPU */
 206     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 207     env->fptag_vmstate = 0;
 208     for(i = 0; i < 8; i++) {
 209         env->fptag_vmstate |= ((!env->fptags[i]) << i);
 210     }
 211
 212     env->fpregs_format_vmstate = 0;
 213
 214     /*
 215      * Real mode guest segments register DPL should be zero.
 216      * Older KVM version were setting it wrongly.
 217      * Fixing it will allow live migration to host with unrestricted guest
 218      * support (otherwise the migration will fail with invalid guest state
 219      * error).
 220      */
 221     if (!(env->cr[0] & CR0_PE_MASK) &&
 222         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 223         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 224         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 225         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 226         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 227         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 228         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 229     }
 230
 231 }
 232
 233 static int cpu_post_load(void *opaque, int version_id)
 234 {
 235     X86CPU *cpu = opaque;
 236     CPUState *cs = CPU(cpu);
 237     CPUX86State *env = &cpu->env;
 238     int i;
 239
 240     if (env->tsc_khz && env->user_tsc_khz &&
 241         env->tsc_khz != env->user_tsc_khz) {
 242         error_report("Mismatch between user-specified TSC frequency and "
 243                      "migrated TSC frequency");
 244         return -EINVAL;
 245     }
 246
 247     if (env->fpregs_format_vmstate) {
 248         error_report("Unsupported old non-softfloat CPU state");
 249         return -EINVAL;
 250     }
 251     /*
 252      * Real mode guest segments register DPL should be zero.
 253      * Older KVM version were setting it wrongly.
 254      * Fixing it will allow live migration from such host that don't have
 255      * restricted guest support to a host with unrestricted guest support
 256      * (otherwise the migration will fail with invalid guest state
 257      * error).
 258      */
 259     if (!(env->cr[0] & CR0_PE_MASK) &&
 260         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 261         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 262         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 263         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 264         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 265         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 266         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 267     }
 268
 269     /* Older versions of QEMU incorrectly used CS.DPL as the CPL when
 270      * running under KVM.  This is wrong for conforming code segments.
 271      * Luckily, in our implementation the CPL field of hflags is redundant
 272      * and we can get the right value from the SS descriptor privilege level.
 273      */
 274     env->hflags &= ~HF_CPL_MASK;
 275     env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 276
 277     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 278     env->fpus = env->fpus_vmstate & ~0x3800;
 279     env->fptag_vmstate ^= 0xff;
 280     for(i = 0; i < 8; i++) {
 281         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 282     }
 283     update_fp_status(env);
 284
 285     cpu_breakpoint_remove_all(cs, BP_CPU);
 286     cpu_watchpoint_remove_all(cs, BP_CPU);
 287     {
 288         /* Indicate all breakpoints disabled, as they are, then
 289            let the helper re-enable them.  */
 290         target_ulong dr7 = env->dr[7];
 291         env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
 292         cpu_x86_update_dr7(env, dr7);
 293     }
 294     tlb_flush(cs);
 295     return 0;
 296 }
 297
 298 static bool async_pf_msr_needed(void *opaque)
 299 {
 300     X86CPU *cpu = opaque;
 301
 302     return cpu->env.async_pf_en_msr != 0;
 303 }
 304
 305 static bool pv_eoi_msr_needed(void *opaque)
 306 {
 307     X86CPU *cpu = opaque;
 308
 309     return cpu->env.pv_eoi_en_msr != 0;
 310 }
 311
 312 static bool steal_time_msr_needed(void *opaque)
 313 {
 314     X86CPU *cpu = opaque;
 315
 316     return cpu->env.steal_time_msr != 0;
 317 }
 318
 319 static const VMStateDescription vmstate_steal_time_msr = {
 320     .name = "cpu/steal_time_msr",
 321     .version_id = 1,
 322     .minimum_version_id = 1,
 323     .needed = steal_time_msr_needed,
 324     .fields = (VMStateField[]) {
 325         VMSTATE_UINT64(env.steal_time_msr, X86CPU),
 326         VMSTATE_END_OF_LIST()
 327     }
 328 };
 329
 330 static const VMStateDescription vmstate_async_pf_msr = {
 331     .name = "cpu/async_pf_msr",
 332     .version_id = 1,
 333     .minimum_version_id = 1,
 334     .needed = async_pf_msr_needed,
 335     .fields = (VMStateField[]) {
 336         VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
 337         VMSTATE_END_OF_LIST()
 338     }
 339 };
 340
 341 static const VMStateDescription vmstate_pv_eoi_msr = {
 342     .name = "cpu/async_pv_eoi_msr",
 343     .version_id = 1,
 344     .minimum_version_id = 1,
 345     .needed = pv_eoi_msr_needed,
 346     .fields = (VMStateField[]) {
 347         VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
 348         VMSTATE_END_OF_LIST()
 349     }
 350 };
 351
 352 static bool fpop_ip_dp_needed(void *opaque)
 353 {
 354     X86CPU *cpu = opaque;
 355     CPUX86State *env = &cpu->env;
 356
 357     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 358 }
 359
 360 static const VMStateDescription vmstate_fpop_ip_dp = {
 361     .name = "cpu/fpop_ip_dp",
 362     .version_id = 1,
 363     .minimum_version_id = 1,
 364     .needed = fpop_ip_dp_needed,
 365     .fields = (VMStateField[]) {
 366         VMSTATE_UINT16(env.fpop, X86CPU),
 367         VMSTATE_UINT64(env.fpip, X86CPU),
 368         VMSTATE_UINT64(env.fpdp, X86CPU),
 369         VMSTATE_END_OF_LIST()
 370     }
 371 };
 372
 373 static bool tsc_adjust_needed(void *opaque)
 374 {
 375     X86CPU *cpu = opaque;
 376     CPUX86State *env = &cpu->env;
 377
 378     return env->tsc_adjust != 0;
 379 }
 380
 381 static const VMStateDescription vmstate_msr_tsc_adjust = {
 382     .name = "cpu/msr_tsc_adjust",
 383     .version_id = 1,
 384     .minimum_version_id = 1,
 385     .needed = tsc_adjust_needed,
 386     .fields = (VMStateField[]) {
 387         VMSTATE_UINT64(env.tsc_adjust, X86CPU),
 388         VMSTATE_END_OF_LIST()
 389     }
 390 };
 391
 392 static bool tscdeadline_needed(void *opaque)
 393 {
 394     X86CPU *cpu = opaque;
 395     CPUX86State *env = &cpu->env;
 396
 397     return env->tsc_deadline != 0;
 398 }
 399
 400 static const VMStateDescription vmstate_msr_tscdeadline = {
 401     .name = "cpu/msr_tscdeadline",
 402     .version_id = 1,
 403     .minimum_version_id = 1,
 404     .needed = tscdeadline_needed,
 405     .fields = (VMStateField[]) {
 406         VMSTATE_UINT64(env.tsc_deadline, X86CPU),
 407         VMSTATE_END_OF_LIST()
 408     }
 409 };
 410
 411 static bool misc_enable_needed(void *opaque)
 412 {
 413     X86CPU *cpu = opaque;
 414     CPUX86State *env = &cpu->env;
 415
 416     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 417 }
 418
 419 static bool feature_control_needed(void *opaque)
 420 {
 421     X86CPU *cpu = opaque;
 422     CPUX86State *env = &cpu->env;
 423
 424     return env->msr_ia32_feature_control != 0;
 425 }
 426
 427 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 428     .name = "cpu/msr_ia32_misc_enable",
 429     .version_id = 1,
 430     .minimum_version_id = 1,
 431     .needed = misc_enable_needed,
 432     .fields = (VMStateField[]) {
 433         VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
 434         VMSTATE_END_OF_LIST()
 435     }
 436 };
 437
 438 static const VMStateDescription vmstate_msr_ia32_feature_control = {
 439     .name = "cpu/msr_ia32_feature_control",
 440     .version_id = 1,
 441     .minimum_version_id = 1,
 442     .needed = feature_control_needed,
 443     .fields = (VMStateField[]) {
 444         VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
 445         VMSTATE_END_OF_LIST()
 446     }
 447 };
 448
 449 static bool pmu_enable_needed(void *opaque)
 450 {
 451     X86CPU *cpu = opaque;
 452     CPUX86State *env = &cpu->env;
 453     int i;
 454
 455     if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
 456         env->msr_global_status || env->msr_global_ovf_ctrl) {
 457         return true;
 458     }
 459     for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
 460         if (env->msr_fixed_counters[i]) {
 461             return true;
 462         }
 463     }
 464     for (i = 0; i < MAX_GP_COUNTERS; i++) {
 465         if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
 466             return true;
 467         }
 468     }
 469
 470     return false;
 471 }
 472
 473 static const VMStateDescription vmstate_msr_architectural_pmu = {
 474     .name = "cpu/msr_architectural_pmu",
 475     .version_id = 1,
 476     .minimum_version_id = 1,
 477     .needed = pmu_enable_needed,
 478     .fields = (VMStateField[]) {
 479         VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
 480         VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
 481         VMSTATE_UINT64(env.msr_global_status, X86CPU),
 482         VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
 483         VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
 484         VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
 485         VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
 486         VMSTATE_END_OF_LIST()
 487     }
 488 };
 489
 490 static bool mpx_needed(void *opaque)
 491 {
 492     X86CPU *cpu = opaque;
 493     CPUX86State *env = &cpu->env;
 494     unsigned int i;
 495
 496     for (i = 0; i < 4; i++) {
 497         if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
 498             return true;
 499         }
 500     }
 501
 502     if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
 503         return true;
 504     }
 505
 506     return !!env->msr_bndcfgs;
 507 }
 508
 509 static const VMStateDescription vmstate_mpx = {
 510     .name = "cpu/mpx",
 511     .version_id = 1,
 512     .minimum_version_id = 1,
 513     .needed = mpx_needed,
 514     .fields = (VMStateField[]) {
 515         VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
 516         VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
 517         VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
 518         VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
 519         VMSTATE_END_OF_LIST()
 520     }
 521 };
 522
 523 static bool hyperv_hypercall_enable_needed(void *opaque)
 524 {
 525     X86CPU *cpu = opaque;
 526     CPUX86State *env = &cpu->env;
 527
 528     return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
 529 }
 530
 531 static const VMStateDescription vmstate_msr_hypercall_hypercall = {
 532     .name = "cpu/msr_hyperv_hypercall",
 533     .version_id = 1,
 534     .minimum_version_id = 1,
 535     .needed = hyperv_hypercall_enable_needed,
 536     .fields = (VMStateField[]) {
 537         VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
 538         VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
 539         VMSTATE_END_OF_LIST()
 540     }
 541 };
 542
 543 static bool hyperv_vapic_enable_needed(void *opaque)
 544 {
 545     X86CPU *cpu = opaque;
 546     CPUX86State *env = &cpu->env;
 547
 548     return env->msr_hv_vapic != 0;
 549 }
 550
 551 static const VMStateDescription vmstate_msr_hyperv_vapic = {
 552     .name = "cpu/msr_hyperv_vapic",
 553     .version_id = 1,
 554     .minimum_version_id = 1,
 555     .needed = hyperv_vapic_enable_needed,
 556     .fields = (VMStateField[]) {
 557         VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
 558         VMSTATE_END_OF_LIST()
 559     }
 560 };
 561
 562 static bool hyperv_time_enable_needed(void *opaque)
 563 {
 564     X86CPU *cpu = opaque;
 565     CPUX86State *env = &cpu->env;
 566
 567     return env->msr_hv_tsc != 0;
 568 }
 569
 570 static const VMStateDescription vmstate_msr_hyperv_time = {
 571     .name = "cpu/msr_hyperv_time",
 572     .version_id = 1,
 573     .minimum_version_id = 1,
 574     .needed = hyperv_time_enable_needed,
 575     .fields = (VMStateField[]) {
 576         VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
 577         VMSTATE_END_OF_LIST()
 578     }
 579 };
 580
 581 static bool hyperv_crash_enable_needed(void *opaque)
 582 {
 583     X86CPU *cpu = opaque;
 584     CPUX86State *env = &cpu->env;
 585     int i;
 586
 587     for (i = 0; i < HV_X64_MSR_CRASH_PARAMS; i++) {
 588         if (env->msr_hv_crash_params[i]) {
 589             return true;
 590         }
 591     }
 592     return false;
 593 }
 594
 595 static const VMStateDescription vmstate_msr_hyperv_crash = {
 596     .name = "cpu/msr_hyperv_crash",
 597     .version_id = 1,
 598     .minimum_version_id = 1,
 599     .needed = hyperv_crash_enable_needed,
 600     .fields = (VMStateField[]) {
 601         VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params,
 602                              X86CPU, HV_X64_MSR_CRASH_PARAMS),
 603         VMSTATE_END_OF_LIST()
 604     }
 605 };
 606
 607 static bool hyperv_runtime_enable_needed(void *opaque)
 608 {
 609     X86CPU *cpu = opaque;
 610     CPUX86State *env = &cpu->env;
 611
 612     if (!cpu->hyperv_runtime) {
 613         return false;
 614     }
 615
 616     return env->msr_hv_runtime != 0;
 617 }
 618
 619 static const VMStateDescription vmstate_msr_hyperv_runtime = {
 620     .name = "cpu/msr_hyperv_runtime",
 621     .version_id = 1,
 622     .minimum_version_id = 1,
 623     .needed = hyperv_runtime_enable_needed,
 624     .fields = (VMStateField[]) {
 625         VMSTATE_UINT64(env.msr_hv_runtime, X86CPU),
 626         VMSTATE_END_OF_LIST()
 627     }
 628 };
 629
 630 static bool hyperv_synic_enable_needed(void *opaque)
 631 {
 632     X86CPU *cpu = opaque;
 633     CPUX86State *env = &cpu->env;
 634     int i;
 635
 636     if (env->msr_hv_synic_control != 0 ||
 637         env->msr_hv_synic_evt_page != 0 ||
 638         env->msr_hv_synic_msg_page != 0) {
 639         return true;
 640     }
 641
 642     for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
 643         if (env->msr_hv_synic_sint[i] != 0) {
 644             return true;
 645         }
 646     }
 647
 648     return false;
 649 }
 650
 651 static const VMStateDescription vmstate_msr_hyperv_synic = {
 652     .name = "cpu/msr_hyperv_synic",
 653     .version_id = 1,
 654     .minimum_version_id = 1,
 655     .needed = hyperv_synic_enable_needed,
 656     .fields = (VMStateField[]) {
 657         VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU),
 658         VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU),
 659         VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU),
 660         VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU,
 661                              HV_SYNIC_SINT_COUNT),
 662         VMSTATE_END_OF_LIST()
 663     }
 664 };
 665
 666 static bool hyperv_stimer_enable_needed(void *opaque)
 667 {
 668     X86CPU *cpu = opaque;
 669     CPUX86State *env = &cpu->env;
 670     int i;
 671
 672     for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) {
 673         if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) {
 674             return true;
 675         }
 676     }
 677     return false;
 678 }
 679
 680 static const VMStateDescription vmstate_msr_hyperv_stimer = {
 681     .name = "cpu/msr_hyperv_stimer",
 682     .version_id = 1,
 683     .minimum_version_id = 1,
 684     .needed = hyperv_stimer_enable_needed,
 685     .fields = (VMStateField[]) {
 686         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config,
 687                              X86CPU, HV_SYNIC_STIMER_COUNT),
 688         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count,
 689                              X86CPU, HV_SYNIC_STIMER_COUNT),
 690         VMSTATE_END_OF_LIST()
 691     }
 692 };
 693
 694 static bool avx512_needed(void *opaque)
 695 {
 696     X86CPU *cpu = opaque;
 697     CPUX86State *env = &cpu->env;
 698     unsigned int i;
 699
 700     for (i = 0; i < NB_OPMASK_REGS; i++) {
 701         if (env->opmask_regs[i]) {
 702             return true;
 703         }
 704     }
 705
 706     for (i = 0; i < CPU_NB_REGS; i++) {
 707 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
 708         if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
 709             ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
 710             return true;
 711         }
 712 #ifdef TARGET_X86_64
 713         if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
 714             ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
 715             ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
 716             ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
 717             return true;
 718         }
 719 #endif
 720     }
 721
 722     return false;
 723 }
 724
 725 static const VMStateDescription vmstate_avx512 = {
 726     .name = "cpu/avx512",
 727     .version_id = 1,
 728     .minimum_version_id = 1,
 729     .needed = avx512_needed,
 730     .fields = (VMStateField[]) {
 731         VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
 732         VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
 733 #ifdef TARGET_X86_64
 734         VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
 735 #endif
 736         VMSTATE_END_OF_LIST()
 737     }
 738 };
 739
 740 static bool xss_needed(void *opaque)
 741 {
 742     X86CPU *cpu = opaque;
 743     CPUX86State *env = &cpu->env;
 744
 745     return env->xss != 0;
 746 }
 747
 748 static const VMStateDescription vmstate_xss = {
 749     .name = "cpu/xss",
 750     .version_id = 1,
 751     .minimum_version_id = 1,
 752     .needed = xss_needed,
 753     .fields = (VMStateField[]) {
 754         VMSTATE_UINT64(env.xss, X86CPU),
 755         VMSTATE_END_OF_LIST()
 756     }
 757 };
 758
 759 #ifdef TARGET_X86_64
 760 static bool pkru_needed(void *opaque)
 761 {
 762     X86CPU *cpu = opaque;
 763     CPUX86State *env = &cpu->env;
 764
 765     return env->pkru != 0;
 766 }
 767
 768 static const VMStateDescription vmstate_pkru = {
 769     .name = "cpu/pkru",
 770     .version_id = 1,
 771     .minimum_version_id = 1,
 772     .needed = pkru_needed,
 773     .fields = (VMStateField[]){
 774         VMSTATE_UINT32(env.pkru, X86CPU),
 775         VMSTATE_END_OF_LIST()
 776     }
 777 };
 778 #endif
 779
 780 static bool tsc_khz_needed(void *opaque)
 781 {
 782     X86CPU *cpu = opaque;
 783     CPUX86State *env = &cpu->env;
 784     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
 785     PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
 786     return env->tsc_khz && pcmc->save_tsc_khz;
 787 }
 788
 789 static const VMStateDescription vmstate_tsc_khz = {
 790     .name = "cpu/tsc_khz",
 791     .version_id = 1,
 792     .minimum_version_id = 1,
 793     .needed = tsc_khz_needed,
 794     .fields = (VMStateField[]) {
 795         VMSTATE_INT64(env.tsc_khz, X86CPU),
 796         VMSTATE_END_OF_LIST()
 797     }
 798 };
 799
 800 static bool mcg_ext_ctl_needed(void *opaque)
 801 {
 802     X86CPU *cpu = opaque;
 803     CPUX86State *env = &cpu->env;
 804     return cpu->enable_lmce && env->mcg_ext_ctl;
 805 }
 806
 807 static const VMStateDescription vmstate_mcg_ext_ctl = {
 808     .name = "cpu/mcg_ext_ctl",
 809     .version_id = 1,
 810     .minimum_version_id = 1,
 811     .needed = mcg_ext_ctl_needed,
 812     .fields = (VMStateField[]) {
 813         VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU),
 814         VMSTATE_END_OF_LIST()
 815     }
 816 };
 817
 818 VMStateDescription vmstate_x86_cpu = {
 819     .name = "cpu",
 820     .version_id = 12,
 821     .minimum_version_id = 11,
 822     .pre_save = cpu_pre_save,
 823     .post_load = cpu_post_load,
 824     .fields = (VMStateField[]) {
 825         VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
 826         VMSTATE_UINTTL(env.eip, X86CPU),
 827         VMSTATE_UINTTL(env.eflags, X86CPU),
 828         VMSTATE_UINT32(env.hflags, X86CPU),
 829         /* FPU */
 830         VMSTATE_UINT16(env.fpuc, X86CPU),
 831         VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
 832         VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
 833         VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
 834
 835         VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPReg),
 836
 837         VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
 838         VMSTATE_SEGMENT(env.ldt, X86CPU),
 839         VMSTATE_SEGMENT(env.tr, X86CPU),
 840         VMSTATE_SEGMENT(env.gdt, X86CPU),
 841         VMSTATE_SEGMENT(env.idt, X86CPU),
 842
 843         VMSTATE_UINT32(env.sysenter_cs, X86CPU),
 844         VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
 845         VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
 846
 847         VMSTATE_UINTTL(env.cr[0], X86CPU),
 848         VMSTATE_UINTTL(env.cr[2], X86CPU),
 849         VMSTATE_UINTTL(env.cr[3], X86CPU),
 850         VMSTATE_UINTTL(env.cr[4], X86CPU),
 851         VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
 852         /* MMU */
 853         VMSTATE_INT32(env.a20_mask, X86CPU),
 854         /* XMM */
 855         VMSTATE_UINT32(env.mxcsr, X86CPU),
 856         VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0),
 857
 858 #ifdef TARGET_X86_64
 859         VMSTATE_UINT64(env.efer, X86CPU),
 860         VMSTATE_UINT64(env.star, X86CPU),
 861         VMSTATE_UINT64(env.lstar, X86CPU),
 862         VMSTATE_UINT64(env.cstar, X86CPU),
 863         VMSTATE_UINT64(env.fmask, X86CPU),
 864         VMSTATE_UINT64(env.kernelgsbase, X86CPU),
 865 #endif
 866         VMSTATE_UINT32(env.smbase, X86CPU),
 867
 868         VMSTATE_UINT64(env.pat, X86CPU),
 869         VMSTATE_UINT32(env.hflags2, X86CPU),
 870
 871         VMSTATE_UINT64(env.vm_hsave, X86CPU),
 872         VMSTATE_UINT64(env.vm_vmcb, X86CPU),
 873         VMSTATE_UINT64(env.tsc_offset, X86CPU),
 874         VMSTATE_UINT64(env.intercept, X86CPU),
 875         VMSTATE_UINT16(env.intercept_cr_read, X86CPU),
 876         VMSTATE_UINT16(env.intercept_cr_write, X86CPU),
 877         VMSTATE_UINT16(env.intercept_dr_read, X86CPU),
 878         VMSTATE_UINT16(env.intercept_dr_write, X86CPU),
 879         VMSTATE_UINT32(env.intercept_exceptions, X86CPU),
 880         VMSTATE_UINT8(env.v_tpr, X86CPU),
 881         /* MTRRs */
 882         VMSTATE_UINT64_ARRAY(env.mtrr_fixed, X86CPU, 11),
 883         VMSTATE_UINT64(env.mtrr_deftype, X86CPU),
 884         VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),
 885         /* KVM-related states */
 886         VMSTATE_INT32(env.interrupt_injected, X86CPU),
 887         VMSTATE_UINT32(env.mp_state, X86CPU),
 888         VMSTATE_UINT64(env.tsc, X86CPU),
 889         VMSTATE_INT32(env.exception_injected, X86CPU),
 890         VMSTATE_UINT8(env.soft_interrupt, X86CPU),
 891         VMSTATE_UINT8(env.nmi_injected, X86CPU),
 892         VMSTATE_UINT8(env.nmi_pending, X86CPU),
 893         VMSTATE_UINT8(env.has_error_code, X86CPU),
 894         VMSTATE_UINT32(env.sipi_vector, X86CPU),
 895         /* MCE */
 896         VMSTATE_UINT64(env.mcg_cap, X86CPU),
 897         VMSTATE_UINT64(env.mcg_status, X86CPU),
 898         VMSTATE_UINT64(env.mcg_ctl, X86CPU),
 899         VMSTATE_UINT64_ARRAY(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4),
 900         /* rdtscp */
 901         VMSTATE_UINT64(env.tsc_aux, X86CPU),
 902         /* KVM pvclock msr */
 903         VMSTATE_UINT64(env.system_time_msr, X86CPU),
 904         VMSTATE_UINT64(env.wall_clock_msr, X86CPU),
 905         /* XSAVE related fields */
 906         VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
 907         VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
 908         VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
 909         VMSTATE_END_OF_LIST()
 910         /* The above list is not sorted /wrt version numbers, watch out! */
 911     },
 912     .subsections = (const VMStateDescription*[]) {
 913         &vmstate_async_pf_msr,
 914         &vmstate_pv_eoi_msr,
 915         &vmstate_steal_time_msr,
 916         &vmstate_fpop_ip_dp,
 917         &vmstate_msr_tsc_adjust,
 918         &vmstate_msr_tscdeadline,
 919         &vmstate_msr_ia32_misc_enable,
 920         &vmstate_msr_ia32_feature_control,
 921         &vmstate_msr_architectural_pmu,
 922         &vmstate_mpx,
 923         &vmstate_msr_hypercall_hypercall,
 924         &vmstate_msr_hyperv_vapic,
 925         &vmstate_msr_hyperv_time,
 926         &vmstate_msr_hyperv_crash,
 927         &vmstate_msr_hyperv_runtime,
 928         &vmstate_msr_hyperv_synic,
 929         &vmstate_msr_hyperv_stimer,
 930         &vmstate_avx512,
 931         &vmstate_xss,
 932         &vmstate_tsc_khz,
 933 #ifdef TARGET_X86_64
 934         &vmstate_pkru,
 935 #endif
 936         &vmstate_mcg_ext_ctl,
 937         NULL
 938     }
 939 };