hw/misc/zynq_slcr.c

   1 /*
   2  * Status and system control registers for Xilinx Zynq Platform
   3  *
   4  * Copyright (c) 2011 Michal Simek <[email protected]>
   5  * Copyright (c) 2012 PetaLogix Pty Ltd.
   6  * Based on hw/arm_sysctl.c, written by Paul Brook
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include "hw/hw.h"
  18 #include "qemu/timer.h"
  19 #include "hw/sysbus.h"
  20 #include "sysemu/sysemu.h"
  21
  22 #ifdef ZYNQ_ARM_SLCR_ERR_DEBUG
  23 #define DB_PRINT(...) do { \
  24     fprintf(stderr,  ": %s: ", __func__); \
  25     fprintf(stderr, ## __VA_ARGS__); \
  26     } while (0);
  27 #else
  28     #define DB_PRINT(...)
  29 #endif
  30
  31 #define XILINX_LOCK_KEY 0x767b
  32 #define XILINX_UNLOCK_KEY 0xdf0d
  33
  34 #define R_PSS_RST_CTRL_SOFT_RST 0x1
  35
  36 enum {
  37     SCL             = 0x000 / 4,
  38     LOCK,
  39     UNLOCK,
  40     LOCKSTA,
  41
  42     ARM_PLL_CTRL    = 0x100 / 4,
  43     DDR_PLL_CTRL,
  44     IO_PLL_CTRL,
  45     PLL_STATUS,
  46     ARM_PLL_CFG,
  47     DDR_PLL_CFG,
  48     IO_PLL_CFG,
  49
  50     ARM_CLK_CTRL    = 0x120 / 4,
  51     DDR_CLK_CTRL,
  52     DCI_CLK_CTRL,
  53     APER_CLK_CTRL,
  54     USB0_CLK_CTRL,
  55     USB1_CLK_CTRL,
  56     GEM0_RCLK_CTRL,
  57     GEM1_RCLK_CTRL,
  58     GEM0_CLK_CTRL,
  59     GEM1_CLK_CTRL,
  60     SMC_CLK_CTRL,
  61     LQSPI_CLK_CTRL,
  62     SDIO_CLK_CTRL,
  63     UART_CLK_CTRL,
  64     SPI_CLK_CTRL,
  65     CAN_CLK_CTRL,
  66     CAN_MIOCLK_CTRL,
  67     DBG_CLK_CTRL,
  68     PCAP_CLK_CTRL,
  69     TOPSW_CLK_CTRL,
  70
  71 #define FPGA_CTRL_REGS(n, start) \
  72     FPGA ## n ## _CLK_CTRL = (start) / 4, \
  73     FPGA ## n ## _THR_CTRL, \
  74     FPGA ## n ## _THR_CNT, \
  75     FPGA ## n ## _THR_STA,
  76     FPGA_CTRL_REGS(0, 0x170)
  77     FPGA_CTRL_REGS(1, 0x180)
  78     FPGA_CTRL_REGS(2, 0x190)
  79     FPGA_CTRL_REGS(3, 0x1a0)
  80
  81     BANDGAP_TRIP    = 0x1b8 / 4,
  82     PLL_PREDIVISOR  = 0x1c0 / 4,
  83     CLK_621_TRUE,
  84
  85     PSS_RST_CTRL    = 0x200 / 4,
  86     DDR_RST_CTRL,
  87     TOPSW_RESET_CTRL,
  88     DMAC_RST_CTRL,
  89     USB_RST_CTRL,
  90     GEM_RST_CTRL,
  91     SDIO_RST_CTRL,
  92     SPI_RST_CTRL,
  93     CAN_RST_CTRL,
  94     I2C_RST_CTRL,
  95     UART_RST_CTRL,
  96     GPIO_RST_CTRL,
  97     LQSPI_RST_CTRL,
  98     SMC_RST_CTRL,
  99     OCM_RST_CTRL,
 100     FPGA_RST_CTRL   = 0x240 / 4,
 101     A9_CPU_RST_CTRL,
 102
 103     RS_AWDT_CTRL    = 0x24c / 4,
 104     RST_REASON,
 105
 106     REBOOT_STATUS   = 0x258 / 4,
 107     BOOT_MODE,
 108
 109     APU_CTRL        = 0x300 / 4,
 110     WDT_CLK_SEL,
 111
 112     TZ_DMA_NS       = 0x440 / 4,
 113     TZ_DMA_IRQ_NS,
 114     TZ_DMA_PERIPH_NS,
 115
 116     PSS_IDCODE      = 0x530 / 4,
 117
 118     DDR_URGENT      = 0x600 / 4,
 119     DDR_CAL_START   = 0x60c / 4,
 120     DDR_REF_START   = 0x614 / 4,
 121     DDR_CMD_STA,
 122     DDR_URGENT_SEL,
 123     DDR_DFI_STATUS,
 124
 125     MIO             = 0x700 / 4,
 126 #define MIO_LENGTH 54
 127
 128     MIO_LOOPBACK    = 0x804 / 4,
 129     MIO_MST_TRI0,
 130     MIO_MST_TRI1,
 131
 132     SD0_WP_CD_SEL   = 0x830 / 4,
 133     SD1_WP_CD_SEL,
 134
 135     LVL_SHFTR_EN    = 0x900 / 4,
 136     OCM_CFG         = 0x910 / 4,
 137
 138     CPU_RAM         = 0xa00 / 4,
 139
 140     IOU             = 0xa30 / 4,
 141
 142     DMAC_RAM        = 0xa50 / 4,
 143
 144     AFI0            = 0xa60 / 4,
 145     AFI1 = AFI0 + 3,
 146     AFI2 = AFI1 + 3,
 147     AFI3 = AFI2 + 3,
 148 #define AFI_LENGTH 3
 149
 150     OCM             = 0xa90 / 4,
 151
 152     DEVCI_RAM       = 0xaa0 / 4,
 153
 154     CSG_RAM         = 0xab0 / 4,
 155
 156     GPIOB_CTRL      = 0xb00 / 4,
 157     GPIOB_CFG_CMOS18,
 158     GPIOB_CFG_CMOS25,
 159     GPIOB_CFG_CMOS33,
 160     GPIOB_CFG_HSTL  = 0xb14 / 4,
 161     GPIOB_DRVR_BIAS_CTRL,
 162
 163     DDRIOB          = 0xb40 / 4,
 164 #define DDRIOB_LENGTH 14
 165 };
 166
 167 #define ZYNQ_SLCR_MMIO_SIZE     0x1000
 168 #define ZYNQ_SLCR_NUM_REGS      (ZYNQ_SLCR_MMIO_SIZE / 4)
 169
 170 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
 171 #define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
 172
 173 typedef struct ZynqSLCRState {
 174     SysBusDevice parent_obj;
 175
 176     MemoryRegion iomem;
 177
 178     uint32_t regs[ZYNQ_SLCR_NUM_REGS];
 179 } ZynqSLCRState;
 180
 181 static void zynq_slcr_reset(DeviceState *d)
 182 {
 183     ZynqSLCRState *s = ZYNQ_SLCR(d);
 184     int i;
 185
 186     DB_PRINT("RESET\n");
 187
 188     s->regs[LOCKSTA] = 1;
 189     /* 0x100 - 0x11C */
 190     s->regs[ARM_PLL_CTRL]   = 0x0001A008;
 191     s->regs[DDR_PLL_CTRL]   = 0x0001A008;
 192     s->regs[IO_PLL_CTRL]    = 0x0001A008;
 193     s->regs[PLL_STATUS]     = 0x0000003F;
 194     s->regs[ARM_PLL_CFG]    = 0x00014000;
 195     s->regs[DDR_PLL_CFG]    = 0x00014000;
 196     s->regs[IO_PLL_CFG]     = 0x00014000;
 197
 198     /* 0x120 - 0x16C */
 199     s->regs[ARM_CLK_CTRL]   = 0x1F000400;
 200     s->regs[DDR_CLK_CTRL]   = 0x18400003;
 201     s->regs[DCI_CLK_CTRL]   = 0x01E03201;
 202     s->regs[APER_CLK_CTRL]  = 0x01FFCCCD;
 203     s->regs[USB0_CLK_CTRL]  = s->regs[USB1_CLK_CTRL]    = 0x00101941;
 204     s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL]   = 0x00000001;
 205     s->regs[GEM0_CLK_CTRL]  = s->regs[GEM1_CLK_CTRL]    = 0x00003C01;
 206     s->regs[SMC_CLK_CTRL]   = 0x00003C01;
 207     s->regs[LQSPI_CLK_CTRL] = 0x00002821;
 208     s->regs[SDIO_CLK_CTRL]  = 0x00001E03;
 209     s->regs[UART_CLK_CTRL]  = 0x00003F03;
 210     s->regs[SPI_CLK_CTRL]   = 0x00003F03;
 211     s->regs[CAN_CLK_CTRL]   = 0x00501903;
 212     s->regs[DBG_CLK_CTRL]   = 0x00000F03;
 213     s->regs[PCAP_CLK_CTRL]  = 0x00000F01;
 214
 215     /* 0x170 - 0x1AC */
 216     s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
 217                             = s->regs[FPGA3_CLK_CTRL] = 0x00101800;
 218     s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
 219                            = s->regs[FPGA3_THR_STA] = 0x00010000;
 220
 221     /* 0x1B0 - 0x1D8 */
 222     s->regs[BANDGAP_TRIP]   = 0x0000001F;
 223     s->regs[PLL_PREDIVISOR] = 0x00000001;
 224     s->regs[CLK_621_TRUE]   = 0x00000001;
 225
 226     /* 0x200 - 0x25C */
 227     s->regs[FPGA_RST_CTRL]  = 0x01F33F0F;
 228     s->regs[RST_REASON]     = 0x00000040;
 229
 230     s->regs[BOOT_MODE]      = 0x00000001;
 231
 232     /* 0x700 - 0x7D4 */
 233     for (i = 0; i < 54; i++) {
 234         s->regs[MIO + i] = 0x00001601;
 235     }
 236     for (i = 2; i <= 8; i++) {
 237         s->regs[MIO + i] = 0x00000601;
 238     }
 239
 240     s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;
 241
 242     s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
 243                          = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
 244                          = 0x00010101;
 245     s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
 246     s->regs[CPU_RAM + 6] = 0x00000001;
 247
 248     s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
 249                      = 0x09090909;
 250     s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
 251     s->regs[IOU + 6] = 0x00000909;
 252
 253     s->regs[DMAC_RAM] = 0x00000009;
 254
 255     s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
 256     s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
 257     s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
 258     s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
 259     s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
 260                       = s->regs[AFI3 + 2] = 0x00000909;
 261
 262     s->regs[OCM + 0]    = 0x01010101;
 263     s->regs[OCM + 1]    = s->regs[OCM + 2] = 0x09090909;
 264
 265     s->regs[DEVCI_RAM]  = 0x00000909;
 266     s->regs[CSG_RAM]    = 0x00000001;
 267
 268     s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
 269                         = s->regs[DDRIOB + 3] = 0x00000e00;
 270     s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
 271                         = 0x00000e00;
 272     s->regs[DDRIOB + 12] = 0x00000021;
 273 }
 274
 275
 276 static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
 277 {
 278     switch (offset) {
 279     case LOCK:
 280     case UNLOCK:
 281     case DDR_CAL_START:
 282     case DDR_REF_START:
 283         return !rnw; /* Write only */
 284     case LOCKSTA:
 285     case FPGA0_THR_STA:
 286     case FPGA1_THR_STA:
 287     case FPGA2_THR_STA:
 288     case FPGA3_THR_STA:
 289     case BOOT_MODE:
 290     case PSS_IDCODE:
 291     case DDR_CMD_STA:
 292     case DDR_DFI_STATUS:
 293     case PLL_STATUS:
 294         return rnw;/* read only */
 295     case SCL:
 296     case ARM_PLL_CTRL ... IO_PLL_CTRL:
 297     case ARM_PLL_CFG ... IO_PLL_CFG:
 298     case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
 299     case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
 300     case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
 301     case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
 302     case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
 303     case BANDGAP_TRIP:
 304     case PLL_PREDIVISOR:
 305     case CLK_621_TRUE:
 306     case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
 307     case RS_AWDT_CTRL:
 308     case RST_REASON:
 309     case REBOOT_STATUS:
 310     case APU_CTRL:
 311     case WDT_CLK_SEL:
 312     case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
 313     case DDR_URGENT:
 314     case DDR_URGENT_SEL:
 315     case MIO ... MIO + MIO_LENGTH - 1:
 316     case MIO_LOOPBACK ... MIO_MST_TRI1:
 317     case SD0_WP_CD_SEL:
 318     case SD1_WP_CD_SEL:
 319     case LVL_SHFTR_EN:
 320     case OCM_CFG:
 321     case CPU_RAM:
 322     case IOU:
 323     case DMAC_RAM:
 324     case AFI0 ... AFI3 + AFI_LENGTH - 1:
 325     case OCM:
 326     case DEVCI_RAM:
 327     case CSG_RAM:
 328     case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
 329     case GPIOB_CFG_HSTL:
 330     case GPIOB_DRVR_BIAS_CTRL:
 331     case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
 332         return true;
 333     default:
 334         return false;
 335     }
 336 }
 337
 338 static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
 339     unsigned size)
 340 {
 341     ZynqSLCRState *s = opaque;
 342     offset /= 4;
 343     uint32_t ret = s->regs[offset];
 344
 345     if (!zynq_slcr_check_offset(offset, true)) {
 346         qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
 347                       " addr %" HWADDR_PRIx "\n", offset * 4);
 348     }
 349
 350     DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret);
 351     return ret;
 352 }
 353
 354 static void zynq_slcr_write(void *opaque, hwaddr offset,
 355                           uint64_t val, unsigned size)
 356 {
 357     ZynqSLCRState *s = (ZynqSLCRState *)opaque;
 358     offset /= 4;
 359
 360     DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);
 361
 362     if (!zynq_slcr_check_offset(offset, false)) {
 363         qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to "
 364                       "addr %" HWADDR_PRIx "\n", offset * 4);
 365         return;
 366     }
 367
 368     switch (offset) {
 369     case SCL:
 370         s->regs[SCL] = val & 0x1;
 371         return;
 372     case LOCK:
 373         if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
 374             DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 375                 (unsigned)val & 0xFFFF);
 376             s->regs[LOCKSTA] = 1;
 377         } else {
 378             DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 379                 (int)offset, (unsigned)val & 0xFFFF);
 380         }
 381         return;
 382     case UNLOCK:
 383         if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
 384             DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 385                 (unsigned)val & 0xFFFF);
 386             s->regs[LOCKSTA] = 0;
 387         } else {
 388             DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 389                 (int)offset, (unsigned)val & 0xFFFF);
 390         }
 391         return;
 392     }
 393
 394     if (!s->regs[LOCKSTA]) {
 395         s->regs[offset / 4] = val;
 396     } else {
 397         DB_PRINT("SCLR registers are locked. Unlock them first\n");
 398         return;
 399     }
 400
 401     switch (offset) {
 402     case PSS_RST_CTRL:
 403         if (val & R_PSS_RST_CTRL_SOFT_RST) {
 404             qemu_system_reset_request();
 405         }
 406         break;
 407     }
 408 }
 409
 410 static const MemoryRegionOps slcr_ops = {
 411     .read = zynq_slcr_read,
 412     .write = zynq_slcr_write,
 413     .endianness = DEVICE_NATIVE_ENDIAN,
 414 };
 415
 416 static int zynq_slcr_init(SysBusDevice *dev)
 417 {
 418     ZynqSLCRState *s = ZYNQ_SLCR(dev);
 419
 420     memory_region_init_io(&s->iomem, OBJECT(s), &slcr_ops, s, "slcr",
 421                           ZYNQ_SLCR_MMIO_SIZE);
 422     sysbus_init_mmio(dev, &s->iomem);
 423
 424     return 0;
 425 }
 426
 427 static const VMStateDescription vmstate_zynq_slcr = {
 428     .name = "zynq_slcr",
 429     .version_id = 2,
 430     .minimum_version_id = 2,
 431     .minimum_version_id_old = 2,
 432     .fields      = (VMStateField[]) {
 433         VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
 434         VMSTATE_END_OF_LIST()
 435     }
 436 };
 437
 438 static void zynq_slcr_class_init(ObjectClass *klass, void *data)
 439 {
 440     DeviceClass *dc = DEVICE_CLASS(klass);
 441     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 442
 443     sdc->init = zynq_slcr_init;
 444     dc->vmsd = &vmstate_zynq_slcr;
 445     dc->reset = zynq_slcr_reset;
 446 }
 447
 448 static const TypeInfo zynq_slcr_info = {
 449     .class_init = zynq_slcr_class_init,
 450     .name  = TYPE_ZYNQ_SLCR,
 451     .parent = TYPE_SYS_BUS_DEVICE,
 452     .instance_size  = sizeof(ZynqSLCRState),
 453 };
 454
 455 static void zynq_slcr_register_types(void)
 456 {
 457     type_register_static(&zynq_slcr_info);
 458 }
 459
 460 type_init(zynq_slcr_register_types)