2 * vfio based device assignment support - PCI devices
4 * Copyright Red Hat, Inc. 2012-2015
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
12 #ifndef HW_VFIO_VFIO_PCI_H
13 #define HW_VFIO_VFIO_PCI_H
15 #include "exec/memory.h"
16 #include "hw/pci/pci.h"
17 #include "hw/vfio/vfio-common.h"
18 #include "qemu/event_notifier.h"
19 #include "qemu/queue.h"
20 #include "qemu/timer.h"
21 #include "qom/object.h"
23 #define PCI_ANY_ID (~0)
27 typedef struct VFIOIOEventFD {
28 QLIST_ENTRY(VFIOIOEventFD) next;
36 bool dynamic; /* Added runtime, removed on device reset */
40 typedef struct VFIOQuirk {
41 QLIST_ENTRY(VFIOQuirk) next;
43 QLIST_HEAD(, VFIOIOEventFD) ioeventfds;
46 void (*reset)(struct VFIOPCIDevice *vdev, struct VFIOQuirk *quirk);
49 typedef struct VFIOBAR {
56 QLIST_HEAD(, VFIOQuirk) quirks;
59 typedef struct VFIOVGARegion {
63 QLIST_HEAD(, VFIOQuirk) quirks;
66 typedef struct VFIOVGA {
69 VFIOVGARegion region[QEMU_PCI_VGA_NUM_REGIONS];
72 typedef struct VFIOINTx {
73 bool pending; /* interrupt pending */
74 bool kvm_accel; /* set when QEMU bypass through KVM enabled */
75 uint8_t pin; /* which pin to pull for qemu_set_irq */
76 EventNotifier interrupt; /* eventfd triggered on interrupt */
77 EventNotifier unmask; /* eventfd for unmask on QEMU bypass */
78 PCIINTxRoute route; /* routing info for QEMU bypass */
79 uint32_t mmap_timeout; /* delay to re-enable mmaps after interrupt */
80 QEMUTimer *mmap_timer; /* enable mmaps after periods w/o interrupts */
83 typedef struct VFIOMSIVector {
85 * Two interrupt paths are configured per vector. The first, is only used
86 * for interrupts injected via QEMU. This is typically the non-accel path,
87 * but may also be used when we want QEMU to handle masking and pending
88 * bits. The KVM path bypasses QEMU and is therefore higher performance,
89 * but requires masking at the device. virq is used to track the MSI route
90 * through KVM, thus kvm_interrupt is only available when virq is set to a
93 EventNotifier interrupt;
94 EventNotifier kvm_interrupt;
95 struct VFIOPCIDevice *vdev; /* back pointer to device */
107 /* Cache of MSI-X setup */
108 typedef struct VFIOMSIXInfo {
112 uint32_t table_offset;
114 unsigned long *pending;
117 #define TYPE_VFIO_PCI "vfio-pci"
118 typedef struct VFIOPCIDevice VFIOPCIDevice;
119 #define PCI_VFIO(obj) OBJECT_CHECK(VFIOPCIDevice, obj, TYPE_VFIO_PCI)
121 struct VFIOPCIDevice {
125 unsigned int config_size;
126 uint8_t *emulated_config_bits; /* QEMU emulated bits, little-endian */
127 off_t config_offset; /* Offset of config space region within device fd */
128 unsigned int rom_size;
129 off_t rom_offset; /* Offset of ROM region within device fd */
132 VFIOMSIVector *msi_vectors;
134 int nr_vectors; /* Number of MSI/MSIX vectors currently in use */
135 int interrupt; /* Current interrupt type */
136 VFIOBAR bars[PCI_NUM_REGIONS - 1]; /* No ROM */
137 VFIOVGA *vga; /* 0xa0000, 0x3b0, 0x3c0 */
139 PCIHostDeviceAddress host;
140 EventNotifier err_notifier;
141 EventNotifier req_notifier;
142 int (*resetfn)(struct VFIOPCIDevice *);
145 uint32_t sub_vendor_id;
146 uint32_t sub_device_id;
148 #define VFIO_FEATURE_ENABLE_VGA_BIT 0
149 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
150 #define VFIO_FEATURE_ENABLE_REQ_BIT 1
151 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
152 #define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2
153 #define VFIO_FEATURE_ENABLE_IGD_OPREGION \
154 (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT)
156 uint32_t display_xres;
157 uint32_t display_yres;
160 OffAutoPCIBAR msix_relo;
162 uint8_t nv_gpudirect_clique;
167 bool rom_read_failed;
171 bool no_geforce_quirks;
172 bool no_kvm_ioeventfd;
173 bool no_vfio_ioeventfd;
176 Error *migration_blocker;
177 Notifier irqchip_change_notifier;
180 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match hw */
181 static inline bool vfio_pci_is(VFIOPCIDevice *vdev, uint32_t vendor, uint32_t device)
183 return (vendor == PCI_ANY_ID || vendor == vdev->vendor_id) &&
184 (device == PCI_ANY_ID || device == vdev->device_id);
187 static inline bool vfio_is_vga(VFIOPCIDevice *vdev)
189 PCIDevice *pdev = &vdev->pdev;
190 uint16_t class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
192 return class == PCI_CLASS_DISPLAY_VGA;
195 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len);
196 void vfio_pci_write_config(PCIDevice *pdev,
197 uint32_t addr, uint32_t val, int len);
199 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size);
200 void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned size);
202 bool vfio_blacklist_opt_rom(VFIOPCIDevice *vdev);
203 void vfio_vga_quirk_setup(VFIOPCIDevice *vdev);
204 void vfio_vga_quirk_exit(VFIOPCIDevice *vdev);
205 void vfio_vga_quirk_finalize(VFIOPCIDevice *vdev);
206 void vfio_bar_quirk_setup(VFIOPCIDevice *vdev, int nr);
207 void vfio_bar_quirk_exit(VFIOPCIDevice *vdev, int nr);
208 void vfio_bar_quirk_finalize(VFIOPCIDevice *vdev, int nr);
209 void vfio_setup_resetfn_quirk(VFIOPCIDevice *vdev);
210 int vfio_add_virt_caps(VFIOPCIDevice *vdev, Error **errp);
211 void vfio_quirk_reset(VFIOPCIDevice *vdev);
212 VFIOQuirk *vfio_quirk_alloc(int nr_mem);
213 void vfio_probe_igd_bar4_quirk(VFIOPCIDevice *vdev, int nr);
215 extern const PropertyInfo qdev_prop_nv_gpudirect_clique;
217 int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp);
219 int vfio_pci_igd_opregion_init(VFIOPCIDevice *vdev,
220 struct vfio_region_info *info,
222 int vfio_pci_nvidia_v100_ram_init(VFIOPCIDevice *vdev, Error **errp);
223 int vfio_pci_nvlink2_init(VFIOPCIDevice *vdev, Error **errp);
225 void vfio_display_reset(VFIOPCIDevice *vdev);
226 int vfio_display_probe(VFIOPCIDevice *vdev, Error **errp);
227 void vfio_display_finalize(VFIOPCIDevice *vdev);
229 #endif /* HW_VFIO_VFIO_PCI_H */