target/openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <[email protected]>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24 #include "exec/exec-all.h"
  25
  26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  27 {
  28     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  29
  30     cpu->env.pc = value;
  31 }
  32
  33 static bool openrisc_cpu_has_work(CPUState *cs)
  34 {
  35     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
  36                                     CPU_INTERRUPT_TIMER);
  37 }
  38
  39 /* CPUClass::reset() */
  40 static void openrisc_cpu_reset(CPUState *s)
  41 {
  42     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  43     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  44
  45     occ->parent_reset(s);
  46
  47     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
  48
  49     cpu->env.pc = 0x100;
  50     cpu->env.sr = SR_FO | SR_SM;
  51     cpu->env.lock_addr = -1;
  52     s->exception_index = -1;
  53
  54     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
  55     cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
  56     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
  57     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
  58
  59 #ifndef CONFIG_USER_ONLY
  60     cpu->env.picmr = 0x00000000;
  61     cpu->env.picsr = 0x00000000;
  62
  63     cpu->env.ttmr = 0x00000000;
  64     cpu->env.ttcr = 0x00000000;
  65 #endif
  66 }
  67
  68 static inline void set_feature(OpenRISCCPU *cpu, int feature)
  69 {
  70     cpu->feature |= feature;
  71     cpu->env.cpucfgr = cpu->feature;
  72 }
  73
  74 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  75 {
  76     CPUState *cs = CPU(dev);
  77     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
  78     Error *local_err = NULL;
  79
  80     cpu_exec_realizefn(cs, &local_err);
  81     if (local_err != NULL) {
  82         error_propagate(errp, local_err);
  83         return;
  84     }
  85
  86     qemu_init_vcpu(cs);
  87     cpu_reset(cs);
  88
  89     occ->parent_realize(dev, errp);
  90 }
  91
  92 static void openrisc_cpu_initfn(Object *obj)
  93 {
  94     CPUState *cs = CPU(obj);
  95     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  96     static int inited;
  97
  98     cs->env_ptr = &cpu->env;
  99
 100 #ifndef CONFIG_USER_ONLY
 101     cpu_openrisc_mmu_init(cpu);
 102 #endif
 103
 104     if (tcg_enabled() && !inited) {
 105         inited = 1;
 106         openrisc_translate_init();
 107     }
 108 }
 109
 110 /* CPU models */
 111
 112 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
 113 {
 114     ObjectClass *oc;
 115     char *typename;
 116
 117     if (cpu_model == NULL) {
 118         return NULL;
 119     }
 120
 121     typename = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, cpu_model);
 122     oc = object_class_by_name(typename);
 123     g_free(typename);
 124     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 125                        object_class_is_abstract(oc))) {
 126         return NULL;
 127     }
 128     return oc;
 129 }
 130
 131 static void or1200_initfn(Object *obj)
 132 {
 133     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 134
 135     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 136     set_feature(cpu, OPENRISC_FEATURE_OF32S);
 137 }
 138
 139 static void openrisc_any_initfn(Object *obj)
 140 {
 141     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 142
 143     set_feature(cpu, OPENRISC_FEATURE_OB32S);
 144 }
 145
 146 typedef struct OpenRISCCPUInfo {
 147     const char *name;
 148     void (*initfn)(Object *obj);
 149 } OpenRISCCPUInfo;
 150
 151 static const OpenRISCCPUInfo openrisc_cpus[] = {
 152     { .name = "or1200",      .initfn = or1200_initfn },
 153     { .name = "any",         .initfn = openrisc_any_initfn },
 154 };
 155
 156 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 157 {
 158     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 159     CPUClass *cc = CPU_CLASS(occ);
 160     DeviceClass *dc = DEVICE_CLASS(oc);
 161
 162     occ->parent_realize = dc->realize;
 163     dc->realize = openrisc_cpu_realizefn;
 164
 165     occ->parent_reset = cc->reset;
 166     cc->reset = openrisc_cpu_reset;
 167
 168     cc->class_by_name = openrisc_cpu_class_by_name;
 169     cc->has_work = openrisc_cpu_has_work;
 170     cc->do_interrupt = openrisc_cpu_do_interrupt;
 171     cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
 172     cc->dump_state = openrisc_cpu_dump_state;
 173     cc->set_pc = openrisc_cpu_set_pc;
 174     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
 175     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 176 #ifdef CONFIG_USER_ONLY
 177     cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
 178 #else
 179     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
 180     dc->vmsd = &vmstate_openrisc_cpu;
 181 #endif
 182     cc->gdb_num_core_regs = 32 + 3;
 183 }
 184
 185 static void cpu_register(const OpenRISCCPUInfo *info)
 186 {
 187     TypeInfo type_info = {
 188         .parent = TYPE_OPENRISC_CPU,
 189         .instance_size = sizeof(OpenRISCCPU),
 190         .instance_init = info->initfn,
 191         .class_size = sizeof(OpenRISCCPUClass),
 192     };
 193
 194     type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
 195     type_register(&type_info);
 196     g_free((void *)type_info.name);
 197 }
 198
 199 static const TypeInfo openrisc_cpu_type_info = {
 200     .name = TYPE_OPENRISC_CPU,
 201     .parent = TYPE_CPU,
 202     .instance_size = sizeof(OpenRISCCPU),
 203     .instance_init = openrisc_cpu_initfn,
 204     .abstract = true,
 205     .class_size = sizeof(OpenRISCCPUClass),
 206     .class_init = openrisc_cpu_class_init,
 207 };
 208
 209 static void openrisc_cpu_register_types(void)
 210 {
 211     int i;
 212
 213     type_register_static(&openrisc_cpu_type_info);
 214     for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
 215         cpu_register(&openrisc_cpus[i]);
 216     }
 217 }
 218
 219 OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
 220 {
 221     return OPENRISC_CPU(cpu_generic_init(TYPE_OPENRISC_CPU, cpu_model));
 222 }
 223
 224 /* Sort alphabetically by type name, except for "any". */
 225 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 226 {
 227     ObjectClass *class_a = (ObjectClass *)a;
 228     ObjectClass *class_b = (ObjectClass *)b;
 229     const char *name_a, *name_b;
 230
 231     name_a = object_class_get_name(class_a);
 232     name_b = object_class_get_name(class_b);
 233     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 234         return 1;
 235     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 236         return -1;
 237     } else {
 238         return strcmp(name_a, name_b);
 239     }
 240 }
 241
 242 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 243 {
 244     ObjectClass *oc = data;
 245     CPUListState *s = user_data;
 246     const char *typename;
 247     char *name;
 248
 249     typename = object_class_get_name(oc);
 250     name = g_strndup(typename,
 251                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 252     (*s->cpu_fprintf)(s->file, "  %s\n",
 253                       name);
 254     g_free(name);
 255 }
 256
 257 void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
 258 {
 259     CPUListState s = {
 260         .file = f,
 261         .cpu_fprintf = cpu_fprintf,
 262     };
 263     GSList *list;
 264
 265     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 266     list = g_slist_sort(list, openrisc_cpu_list_compare);
 267     (*cpu_fprintf)(f, "Available CPUs:\n");
 268     g_slist_foreach(list, openrisc_cpu_list_entry, &s);
 269     g_slist_free(list);
 270 }
 271
 272 type_init(openrisc_cpu_register_types)