hw/block/nvme.c

   1 /*
   2  * QEMU NVM Express Controller
   3  *
   4  * Copyright (c) 2012, Intel Corporation
   5  *
   6  * Written by Keith Busch <[email protected]>
   7  *
   8  * This code is licensed under the GNU GPL v2 or later.
   9  */
  10
  11 /**
  12  * Reference Specs: http://www.nvmexpress.org, 1.2, 1.1, 1.0e
  13  *
  14  *  http://www.nvmexpress.org/resources/
  15  */
  16
  17 /**
  18  * Usage: add options:
  19  *      -drive file=<file>,if=none,id=<drive_id>
  20  *      -device nvme,drive=<drive_id>,serial=<serial>,id=<id[optional]>, \
  21  *              cmb_size_mb=<cmb_size_mb[optional]>, \
  22  *              [pmrdev=<mem_backend_file_id>,] \
  23  *              num_queues=<N[optional]>
  24  *
  25  * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at
  26  * offset 0 in BAR2 and supports only WDS, RDS and SQS for now.
  27  *
  28  * cmb_size_mb= and pmrdev= options are mutually exclusive due to limitation
  29  * in available BAR's. cmb_size_mb= will take precedence over pmrdev= when
  30  * both provided.
  31  * Enabling pmr emulation can be achieved by pointing to memory-backend-file.
  32  * For example:
  33  * -object memory-backend-file,id=<mem_id>,share=on,mem-path=<file_path>, \
  34  *  size=<size> .... -device nvme,...,pmrdev=<mem_id>
  35  */
  36
  37 #include "qemu/osdep.h"
  38 #include "qemu/units.h"
  39 #include "hw/block/block.h"
  40 #include "hw/pci/msix.h"
  41 #include "hw/pci/pci.h"
  42 #include "hw/qdev-properties.h"
  43 #include "migration/vmstate.h"
  44 #include "sysemu/sysemu.h"
  45 #include "qapi/error.h"
  46 #include "qapi/visitor.h"
  47 #include "sysemu/hostmem.h"
  48 #include "sysemu/block-backend.h"
  49 #include "exec/memory.h"
  50 #include "qemu/log.h"
  51 #include "qemu/module.h"
  52 #include "qemu/cutils.h"
  53 #include "trace.h"
  54 #include "nvme.h"
  55
  56 #define NVME_GUEST_ERR(trace, fmt, ...) \
  57     do { \
  58         (trace_##trace)(__VA_ARGS__); \
  59         qemu_log_mask(LOG_GUEST_ERROR, #trace \
  60             " in %s: " fmt "\n", __func__, ## __VA_ARGS__); \
  61     } while (0)
  62
  63 static void nvme_process_sq(void *opaque);
  64
  65 static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
  66 {
  67     if (n->cmbsz && addr >= n->ctrl_mem.addr &&
  68                 addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))) {
  69         memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size);
  70     } else {
  71         pci_dma_read(&n->parent_obj, addr, buf, size);
  72     }
  73 }
  74
  75 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid)
  76 {
  77     return sqid < n->num_queues && n->sq[sqid] != NULL ? 0 : -1;
  78 }
  79
  80 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid)
  81 {
  82     return cqid < n->num_queues && n->cq[cqid] != NULL ? 0 : -1;
  83 }
  84
  85 static void nvme_inc_cq_tail(NvmeCQueue *cq)
  86 {
  87     cq->tail++;
  88     if (cq->tail >= cq->size) {
  89         cq->tail = 0;
  90         cq->phase = !cq->phase;
  91     }
  92 }
  93
  94 static void nvme_inc_sq_head(NvmeSQueue *sq)
  95 {
  96     sq->head = (sq->head + 1) % sq->size;
  97 }
  98
  99 static uint8_t nvme_cq_full(NvmeCQueue *cq)
 100 {
 101     return (cq->tail + 1) % cq->size == cq->head;
 102 }
 103
 104 static uint8_t nvme_sq_empty(NvmeSQueue *sq)
 105 {
 106     return sq->head == sq->tail;
 107 }
 108
 109 static void nvme_irq_check(NvmeCtrl *n)
 110 {
 111     if (msix_enabled(&(n->parent_obj))) {
 112         return;
 113     }
 114     if (~n->bar.intms & n->irq_status) {
 115         pci_irq_assert(&n->parent_obj);
 116     } else {
 117         pci_irq_deassert(&n->parent_obj);
 118     }
 119 }
 120
 121 static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
 122 {
 123     if (cq->irq_enabled) {
 124         if (msix_enabled(&(n->parent_obj))) {
 125             trace_nvme_irq_msix(cq->vector);
 126             msix_notify(&(n->parent_obj), cq->vector);
 127         } else {
 128             trace_nvme_irq_pin();
 129             assert(cq->cqid < 64);
 130             n->irq_status |= 1 << cq->cqid;
 131             nvme_irq_check(n);
 132         }
 133     } else {
 134         trace_nvme_irq_masked();
 135     }
 136 }
 137
 138 static void nvme_irq_deassert(NvmeCtrl *n, NvmeCQueue *cq)
 139 {
 140     if (cq->irq_enabled) {
 141         if (msix_enabled(&(n->parent_obj))) {
 142             return;
 143         } else {
 144             assert(cq->cqid < 64);
 145             n->irq_status &= ~(1 << cq->cqid);
 146             nvme_irq_check(n);
 147         }
 148     }
 149 }
 150
 151 static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVector *iov, uint64_t prp1,
 152                              uint64_t prp2, uint32_t len, NvmeCtrl *n)
 153 {
 154     hwaddr trans_len = n->page_size - (prp1 % n->page_size);
 155     trans_len = MIN(len, trans_len);
 156     int num_prps = (len >> n->page_bits) + 1;
 157
 158     if (unlikely(!prp1)) {
 159         trace_nvme_err_invalid_prp();
 160         return NVME_INVALID_FIELD | NVME_DNR;
 161     } else if (n->cmbsz && prp1 >= n->ctrl_mem.addr &&
 162                prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) {
 163         qsg->nsg = 0;
 164         qemu_iovec_init(iov, num_prps);
 165         qemu_iovec_add(iov, (void *)&n->cmbuf[prp1 - n->ctrl_mem.addr], trans_len);
 166     } else {
 167         pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
 168         qemu_sglist_add(qsg, prp1, trans_len);
 169     }
 170     len -= trans_len;
 171     if (len) {
 172         if (unlikely(!prp2)) {
 173             trace_nvme_err_invalid_prp2_missing();
 174             goto unmap;
 175         }
 176         if (len > n->page_size) {
 177             uint64_t prp_list[n->max_prp_ents];
 178             uint32_t nents, prp_trans;
 179             int i = 0;
 180
 181             nents = (len + n->page_size - 1) >> n->page_bits;
 182             prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
 183             nvme_addr_read(n, prp2, (void *)prp_list, prp_trans);
 184             while (len != 0) {
 185                 uint64_t prp_ent = le64_to_cpu(prp_list[i]);
 186
 187                 if (i == n->max_prp_ents - 1 && len > n->page_size) {
 188                     if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
 189                         trace_nvme_err_invalid_prplist_ent(prp_ent);
 190                         goto unmap;
 191                     }
 192
 193                     i = 0;
 194                     nents = (len + n->page_size - 1) >> n->page_bits;
 195                     prp_trans = MIN(n->max_prp_ents, nents) * sizeof(uint64_t);
 196                     nvme_addr_read(n, prp_ent, (void *)prp_list,
 197                         prp_trans);
 198                     prp_ent = le64_to_cpu(prp_list[i]);
 199                 }
 200
 201                 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) {
 202                     trace_nvme_err_invalid_prplist_ent(prp_ent);
 203                     goto unmap;
 204                 }
 205
 206                 trans_len = MIN(len, n->page_size);
 207                 if (qsg->nsg){
 208                     qemu_sglist_add(qsg, prp_ent, trans_len);
 209                 } else {
 210                     qemu_iovec_add(iov, (void *)&n->cmbuf[prp_ent - n->ctrl_mem.addr], trans_len);
 211                 }
 212                 len -= trans_len;
 213                 i++;
 214             }
 215         } else {
 216             if (unlikely(prp2 & (n->page_size - 1))) {
 217                 trace_nvme_err_invalid_prp2_align(prp2);
 218                 goto unmap;
 219             }
 220             if (qsg->nsg) {
 221                 qemu_sglist_add(qsg, prp2, len);
 222             } else {
 223                 qemu_iovec_add(iov, (void *)&n->cmbuf[prp2 - n->ctrl_mem.addr], trans_len);
 224             }
 225         }
 226     }
 227     return NVME_SUCCESS;
 228
 229  unmap:
 230     qemu_sglist_destroy(qsg);
 231     return NVME_INVALID_FIELD | NVME_DNR;
 232 }
 233
 234 static uint16_t nvme_dma_write_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
 235                                    uint64_t prp1, uint64_t prp2)
 236 {
 237     QEMUSGList qsg;
 238     QEMUIOVector iov;
 239     uint16_t status = NVME_SUCCESS;
 240
 241     if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
 242         return NVME_INVALID_FIELD | NVME_DNR;
 243     }
 244     if (qsg.nsg > 0) {
 245         if (dma_buf_write(ptr, len, &qsg)) {
 246             status = NVME_INVALID_FIELD | NVME_DNR;
 247         }
 248         qemu_sglist_destroy(&qsg);
 249     } else {
 250         if (qemu_iovec_to_buf(&iov, 0, ptr, len) != len) {
 251             status = NVME_INVALID_FIELD | NVME_DNR;
 252         }
 253         qemu_iovec_destroy(&iov);
 254     }
 255     return status;
 256 }
 257
 258 static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
 259     uint64_t prp1, uint64_t prp2)
 260 {
 261     QEMUSGList qsg;
 262     QEMUIOVector iov;
 263     uint16_t status = NVME_SUCCESS;
 264
 265     trace_nvme_dma_read(prp1, prp2);
 266
 267     if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) {
 268         return NVME_INVALID_FIELD | NVME_DNR;
 269     }
 270     if (qsg.nsg > 0) {
 271         if (unlikely(dma_buf_read(ptr, len, &qsg))) {
 272             trace_nvme_err_invalid_dma();
 273             status = NVME_INVALID_FIELD | NVME_DNR;
 274         }
 275         qemu_sglist_destroy(&qsg);
 276     } else {
 277         if (unlikely(qemu_iovec_from_buf(&iov, 0, ptr, len) != len)) {
 278             trace_nvme_err_invalid_dma();
 279             status = NVME_INVALID_FIELD | NVME_DNR;
 280         }
 281         qemu_iovec_destroy(&iov);
 282     }
 283     return status;
 284 }
 285
 286 static void nvme_post_cqes(void *opaque)
 287 {
 288     NvmeCQueue *cq = opaque;
 289     NvmeCtrl *n = cq->ctrl;
 290     NvmeRequest *req, *next;
 291
 292     QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
 293         NvmeSQueue *sq;
 294         hwaddr addr;
 295
 296         if (nvme_cq_full(cq)) {
 297             break;
 298         }
 299
 300         QTAILQ_REMOVE(&cq->req_list, req, entry);
 301         sq = req->sq;
 302         req->cqe.status = cpu_to_le16((req->status << 1) | cq->phase);
 303         req->cqe.sq_id = cpu_to_le16(sq->sqid);
 304         req->cqe.sq_head = cpu_to_le16(sq->head);
 305         addr = cq->dma_addr + cq->tail * n->cqe_size;
 306         nvme_inc_cq_tail(cq);
 307         pci_dma_write(&n->parent_obj, addr, (void *)&req->cqe,
 308             sizeof(req->cqe));
 309         QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
 310     }
 311     if (cq->tail != cq->head) {
 312         nvme_irq_assert(n, cq);
 313     }
 314 }
 315
 316 static void nvme_enqueue_req_completion(NvmeCQueue *cq, NvmeRequest *req)
 317 {
 318     assert(cq->cqid == req->sq->cqid);
 319     QTAILQ_REMOVE(&req->sq->out_req_list, req, entry);
 320     QTAILQ_INSERT_TAIL(&cq->req_list, req, entry);
 321     timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
 322 }
 323
 324 static void nvme_rw_cb(void *opaque, int ret)
 325 {
 326     NvmeRequest *req = opaque;
 327     NvmeSQueue *sq = req->sq;
 328     NvmeCtrl *n = sq->ctrl;
 329     NvmeCQueue *cq = n->cq[sq->cqid];
 330
 331     if (!ret) {
 332         block_acct_done(blk_get_stats(n->conf.blk), &req->acct);
 333         req->status = NVME_SUCCESS;
 334     } else {
 335         block_acct_failed(blk_get_stats(n->conf.blk), &req->acct);
 336         req->status = NVME_INTERNAL_DEV_ERROR;
 337     }
 338     if (req->has_sg) {
 339         qemu_sglist_destroy(&req->qsg);
 340     }
 341     nvme_enqueue_req_completion(cq, req);
 342 }
 343
 344 static uint16_t nvme_flush(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
 345     NvmeRequest *req)
 346 {
 347     req->has_sg = false;
 348     block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
 349          BLOCK_ACCT_FLUSH);
 350     req->aiocb = blk_aio_flush(n->conf.blk, nvme_rw_cb, req);
 351
 352     return NVME_NO_COMPLETE;
 353 }
 354
 355 static uint16_t nvme_write_zeros(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
 356     NvmeRequest *req)
 357 {
 358     NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
 359     const uint8_t lba_index = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
 360     const uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
 361     uint64_t slba = le64_to_cpu(rw->slba);
 362     uint32_t nlb  = le16_to_cpu(rw->nlb) + 1;
 363     uint64_t offset = slba << data_shift;
 364     uint32_t count = nlb << data_shift;
 365
 366     if (unlikely(slba + nlb > ns->id_ns.nsze)) {
 367         trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
 368         return NVME_LBA_RANGE | NVME_DNR;
 369     }
 370
 371     req->has_sg = false;
 372     block_acct_start(blk_get_stats(n->conf.blk), &req->acct, 0,
 373                      BLOCK_ACCT_WRITE);
 374     req->aiocb = blk_aio_pwrite_zeroes(n->conf.blk, offset, count,
 375                                         BDRV_REQ_MAY_UNMAP, nvme_rw_cb, req);
 376     return NVME_NO_COMPLETE;
 377 }
 378
 379 static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *ns, NvmeCmd *cmd,
 380     NvmeRequest *req)
 381 {
 382     NvmeRwCmd *rw = (NvmeRwCmd *)cmd;
 383     uint32_t nlb  = le32_to_cpu(rw->nlb) + 1;
 384     uint64_t slba = le64_to_cpu(rw->slba);
 385     uint64_t prp1 = le64_to_cpu(rw->prp1);
 386     uint64_t prp2 = le64_to_cpu(rw->prp2);
 387
 388     uint8_t lba_index  = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
 389     uint8_t data_shift = ns->id_ns.lbaf[lba_index].ds;
 390     uint64_t data_size = (uint64_t)nlb << data_shift;
 391     uint64_t data_offset = slba << data_shift;
 392     int is_write = rw->opcode == NVME_CMD_WRITE ? 1 : 0;
 393     enum BlockAcctType acct = is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_READ;
 394
 395     trace_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba);
 396
 397     if (unlikely((slba + nlb) > ns->id_ns.nsze)) {
 398         block_acct_invalid(blk_get_stats(n->conf.blk), acct);
 399         trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze);
 400         return NVME_LBA_RANGE | NVME_DNR;
 401     }
 402
 403     if (nvme_map_prp(&req->qsg, &req->iov, prp1, prp2, data_size, n)) {
 404         block_acct_invalid(blk_get_stats(n->conf.blk), acct);
 405         return NVME_INVALID_FIELD | NVME_DNR;
 406     }
 407
 408     dma_acct_start(n->conf.blk, &req->acct, &req->qsg, acct);
 409     if (req->qsg.nsg > 0) {
 410         req->has_sg = true;
 411         req->aiocb = is_write ?
 412             dma_blk_write(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
 413                           nvme_rw_cb, req) :
 414             dma_blk_read(n->conf.blk, &req->qsg, data_offset, BDRV_SECTOR_SIZE,
 415                          nvme_rw_cb, req);
 416     } else {
 417         req->has_sg = false;
 418         req->aiocb = is_write ?
 419             blk_aio_pwritev(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
 420                             req) :
 421             blk_aio_preadv(n->conf.blk, data_offset, &req->iov, 0, nvme_rw_cb,
 422                            req);
 423     }
 424
 425     return NVME_NO_COMPLETE;
 426 }
 427
 428 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 429 {
 430     NvmeNamespace *ns;
 431     uint32_t nsid = le32_to_cpu(cmd->nsid);
 432
 433     if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
 434         trace_nvme_err_invalid_ns(nsid, n->num_namespaces);
 435         return NVME_INVALID_NSID | NVME_DNR;
 436     }
 437
 438     ns = &n->namespaces[nsid - 1];
 439     switch (cmd->opcode) {
 440     case NVME_CMD_FLUSH:
 441         return nvme_flush(n, ns, cmd, req);
 442     case NVME_CMD_WRITE_ZEROS:
 443         return nvme_write_zeros(n, ns, cmd, req);
 444     case NVME_CMD_WRITE:
 445     case NVME_CMD_READ:
 446         return nvme_rw(n, ns, cmd, req);
 447     default:
 448         trace_nvme_err_invalid_opc(cmd->opcode);
 449         return NVME_INVALID_OPCODE | NVME_DNR;
 450     }
 451 }
 452
 453 static void nvme_free_sq(NvmeSQueue *sq, NvmeCtrl *n)
 454 {
 455     n->sq[sq->sqid] = NULL;
 456     timer_del(sq->timer);
 457     timer_free(sq->timer);
 458     g_free(sq->io_req);
 459     if (sq->sqid) {
 460         g_free(sq);
 461     }
 462 }
 463
 464 static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd)
 465 {
 466     NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
 467     NvmeRequest *req, *next;
 468     NvmeSQueue *sq;
 469     NvmeCQueue *cq;
 470     uint16_t qid = le16_to_cpu(c->qid);
 471
 472     if (unlikely(!qid || nvme_check_sqid(n, qid))) {
 473         trace_nvme_err_invalid_del_sq(qid);
 474         return NVME_INVALID_QID | NVME_DNR;
 475     }
 476
 477     trace_nvme_del_sq(qid);
 478
 479     sq = n->sq[qid];
 480     while (!QTAILQ_EMPTY(&sq->out_req_list)) {
 481         req = QTAILQ_FIRST(&sq->out_req_list);
 482         assert(req->aiocb);
 483         blk_aio_cancel(req->aiocb);
 484     }
 485     if (!nvme_check_cqid(n, sq->cqid)) {
 486         cq = n->cq[sq->cqid];
 487         QTAILQ_REMOVE(&cq->sq_list, sq, entry);
 488
 489         nvme_post_cqes(cq);
 490         QTAILQ_FOREACH_SAFE(req, &cq->req_list, entry, next) {
 491             if (req->sq == sq) {
 492                 QTAILQ_REMOVE(&cq->req_list, req, entry);
 493                 QTAILQ_INSERT_TAIL(&sq->req_list, req, entry);
 494             }
 495         }
 496     }
 497
 498     nvme_free_sq(sq, n);
 499     return NVME_SUCCESS;
 500 }
 501
 502 static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl *n, uint64_t dma_addr,
 503     uint16_t sqid, uint16_t cqid, uint16_t size)
 504 {
 505     int i;
 506     NvmeCQueue *cq;
 507
 508     sq->ctrl = n;
 509     sq->dma_addr = dma_addr;
 510     sq->sqid = sqid;
 511     sq->size = size;
 512     sq->cqid = cqid;
 513     sq->head = sq->tail = 0;
 514     sq->io_req = g_new(NvmeRequest, sq->size);
 515
 516     QTAILQ_INIT(&sq->req_list);
 517     QTAILQ_INIT(&sq->out_req_list);
 518     for (i = 0; i < sq->size; i++) {
 519         sq->io_req[i].sq = sq;
 520         QTAILQ_INSERT_TAIL(&(sq->req_list), &sq->io_req[i], entry);
 521     }
 522     sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
 523
 524     assert(n->cq[cqid]);
 525     cq = n->cq[cqid];
 526     QTAILQ_INSERT_TAIL(&(cq->sq_list), sq, entry);
 527     n->sq[sqid] = sq;
 528 }
 529
 530 static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *cmd)
 531 {
 532     NvmeSQueue *sq;
 533     NvmeCreateSq *c = (NvmeCreateSq *)cmd;
 534
 535     uint16_t cqid = le16_to_cpu(c->cqid);
 536     uint16_t sqid = le16_to_cpu(c->sqid);
 537     uint16_t qsize = le16_to_cpu(c->qsize);
 538     uint16_t qflags = le16_to_cpu(c->sq_flags);
 539     uint64_t prp1 = le64_to_cpu(c->prp1);
 540
 541     trace_nvme_create_sq(prp1, sqid, cqid, qsize, qflags);
 542
 543     if (unlikely(!cqid || nvme_check_cqid(n, cqid))) {
 544         trace_nvme_err_invalid_create_sq_cqid(cqid);
 545         return NVME_INVALID_CQID | NVME_DNR;
 546     }
 547     if (unlikely(!sqid || !nvme_check_sqid(n, sqid))) {
 548         trace_nvme_err_invalid_create_sq_sqid(sqid);
 549         return NVME_INVALID_QID | NVME_DNR;
 550     }
 551     if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
 552         trace_nvme_err_invalid_create_sq_size(qsize);
 553         return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
 554     }
 555     if (unlikely(!prp1 || prp1 & (n->page_size - 1))) {
 556         trace_nvme_err_invalid_create_sq_addr(prp1);
 557         return NVME_INVALID_FIELD | NVME_DNR;
 558     }
 559     if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) {
 560         trace_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags));
 561         return NVME_INVALID_FIELD | NVME_DNR;
 562     }
 563     sq = g_malloc0(sizeof(*sq));
 564     nvme_init_sq(sq, n, prp1, sqid, cqid, qsize + 1);
 565     return NVME_SUCCESS;
 566 }
 567
 568 static void nvme_free_cq(NvmeCQueue *cq, NvmeCtrl *n)
 569 {
 570     n->cq[cq->cqid] = NULL;
 571     timer_del(cq->timer);
 572     timer_free(cq->timer);
 573     msix_vector_unuse(&n->parent_obj, cq->vector);
 574     if (cq->cqid) {
 575         g_free(cq);
 576     }
 577 }
 578
 579 static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd)
 580 {
 581     NvmeDeleteQ *c = (NvmeDeleteQ *)cmd;
 582     NvmeCQueue *cq;
 583     uint16_t qid = le16_to_cpu(c->qid);
 584
 585     if (unlikely(!qid || nvme_check_cqid(n, qid))) {
 586         trace_nvme_err_invalid_del_cq_cqid(qid);
 587         return NVME_INVALID_CQID | NVME_DNR;
 588     }
 589
 590     cq = n->cq[qid];
 591     if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) {
 592         trace_nvme_err_invalid_del_cq_notempty(qid);
 593         return NVME_INVALID_QUEUE_DEL;
 594     }
 595     nvme_irq_deassert(n, cq);
 596     trace_nvme_del_cq(qid);
 597     nvme_free_cq(cq, n);
 598     return NVME_SUCCESS;
 599 }
 600
 601 static void nvme_init_cq(NvmeCQueue *cq, NvmeCtrl *n, uint64_t dma_addr,
 602     uint16_t cqid, uint16_t vector, uint16_t size, uint16_t irq_enabled)
 603 {
 604     cq->ctrl = n;
 605     cq->cqid = cqid;
 606     cq->size = size;
 607     cq->dma_addr = dma_addr;
 608     cq->phase = 1;
 609     cq->irq_enabled = irq_enabled;
 610     cq->vector = vector;
 611     cq->head = cq->tail = 0;
 612     QTAILQ_INIT(&cq->req_list);
 613     QTAILQ_INIT(&cq->sq_list);
 614     msix_vector_use(&n->parent_obj, cq->vector);
 615     n->cq[cqid] = cq;
 616     cq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_post_cqes, cq);
 617 }
 618
 619 static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cmd)
 620 {
 621     NvmeCQueue *cq;
 622     NvmeCreateCq *c = (NvmeCreateCq *)cmd;
 623     uint16_t cqid = le16_to_cpu(c->cqid);
 624     uint16_t vector = le16_to_cpu(c->irq_vector);
 625     uint16_t qsize = le16_to_cpu(c->qsize);
 626     uint16_t qflags = le16_to_cpu(c->cq_flags);
 627     uint64_t prp1 = le64_to_cpu(c->prp1);
 628
 629     trace_nvme_create_cq(prp1, cqid, vector, qsize, qflags,
 630                          NVME_CQ_FLAGS_IEN(qflags) != 0);
 631
 632     if (unlikely(!cqid || !nvme_check_cqid(n, cqid))) {
 633         trace_nvme_err_invalid_create_cq_cqid(cqid);
 634         return NVME_INVALID_CQID | NVME_DNR;
 635     }
 636     if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) {
 637         trace_nvme_err_invalid_create_cq_size(qsize);
 638         return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR;
 639     }
 640     if (unlikely(!prp1)) {
 641         trace_nvme_err_invalid_create_cq_addr(prp1);
 642         return NVME_INVALID_FIELD | NVME_DNR;
 643     }
 644     if (unlikely(vector > n->num_queues)) {
 645         trace_nvme_err_invalid_create_cq_vector(vector);
 646         return NVME_INVALID_IRQ_VECTOR | NVME_DNR;
 647     }
 648     if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) {
 649         trace_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags));
 650         return NVME_INVALID_FIELD | NVME_DNR;
 651     }
 652
 653     cq = g_malloc0(sizeof(*cq));
 654     nvme_init_cq(cq, n, prp1, cqid, vector, qsize + 1,
 655         NVME_CQ_FLAGS_IEN(qflags));
 656     return NVME_SUCCESS;
 657 }
 658
 659 static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIdentify *c)
 660 {
 661     uint64_t prp1 = le64_to_cpu(c->prp1);
 662     uint64_t prp2 = le64_to_cpu(c->prp2);
 663
 664     trace_nvme_identify_ctrl();
 665
 666     return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
 667         prp1, prp2);
 668 }
 669
 670 static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdentify *c)
 671 {
 672     NvmeNamespace *ns;
 673     uint32_t nsid = le32_to_cpu(c->nsid);
 674     uint64_t prp1 = le64_to_cpu(c->prp1);
 675     uint64_t prp2 = le64_to_cpu(c->prp2);
 676
 677     trace_nvme_identify_ns(nsid);
 678
 679     if (unlikely(nsid == 0 || nsid > n->num_namespaces)) {
 680         trace_nvme_err_invalid_ns(nsid, n->num_namespaces);
 681         return NVME_INVALID_NSID | NVME_DNR;
 682     }
 683
 684     ns = &n->namespaces[nsid - 1];
 685
 686     return nvme_dma_read_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
 687         prp1, prp2);
 688 }
 689
 690 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c)
 691 {
 692     static const int data_len = 4 * KiB;
 693     uint32_t min_nsid = le32_to_cpu(c->nsid);
 694     uint64_t prp1 = le64_to_cpu(c->prp1);
 695     uint64_t prp2 = le64_to_cpu(c->prp2);
 696     uint32_t *list;
 697     uint16_t ret;
 698     int i, j = 0;
 699
 700     trace_nvme_identify_nslist(min_nsid);
 701
 702     list = g_malloc0(data_len);
 703     for (i = 0; i < n->num_namespaces; i++) {
 704         if (i < min_nsid) {
 705             continue;
 706         }
 707         list[j++] = cpu_to_le32(i + 1);
 708         if (j == data_len / sizeof(uint32_t)) {
 709             break;
 710         }
 711     }
 712     ret = nvme_dma_read_prp(n, (uint8_t *)list, data_len, prp1, prp2);
 713     g_free(list);
 714     return ret;
 715 }
 716
 717 static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *cmd)
 718 {
 719     NvmeIdentify *c = (NvmeIdentify *)cmd;
 720
 721     switch (le32_to_cpu(c->cns)) {
 722     case 0x00:
 723         return nvme_identify_ns(n, c);
 724     case 0x01:
 725         return nvme_identify_ctrl(n, c);
 726     case 0x02:
 727         return nvme_identify_nslist(n, c);
 728     default:
 729         trace_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns));
 730         return NVME_INVALID_FIELD | NVME_DNR;
 731     }
 732 }
 733
 734 static inline void nvme_set_timestamp(NvmeCtrl *n, uint64_t ts)
 735 {
 736     trace_nvme_setfeat_timestamp(ts);
 737
 738     n->host_timestamp = le64_to_cpu(ts);
 739     n->timestamp_set_qemu_clock_ms = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
 740 }
 741
 742 static inline uint64_t nvme_get_timestamp(const NvmeCtrl *n)
 743 {
 744     uint64_t current_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
 745     uint64_t elapsed_time = current_time - n->timestamp_set_qemu_clock_ms;
 746
 747     union nvme_timestamp {
 748         struct {
 749             uint64_t timestamp:48;
 750             uint64_t sync:1;
 751             uint64_t origin:3;
 752             uint64_t rsvd1:12;
 753         };
 754         uint64_t all;
 755     };
 756
 757     union nvme_timestamp ts;
 758     ts.all = 0;
 759
 760     /*
 761      * If the sum of the Timestamp value set by the host and the elapsed
 762      * time exceeds 2^48, the value returned should be reduced modulo 2^48.
 763      */
 764     ts.timestamp = (n->host_timestamp + elapsed_time) & 0xffffffffffff;
 765
 766     /* If the host timestamp is non-zero, set the timestamp origin */
 767     ts.origin = n->host_timestamp ? 0x01 : 0x00;
 768
 769     trace_nvme_getfeat_timestamp(ts.all);
 770
 771     return cpu_to_le64(ts.all);
 772 }
 773
 774 static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd)
 775 {
 776     uint64_t prp1 = le64_to_cpu(cmd->prp1);
 777     uint64_t prp2 = le64_to_cpu(cmd->prp2);
 778
 779     uint64_t timestamp = nvme_get_timestamp(n);
 780
 781     return nvme_dma_read_prp(n, (uint8_t *)&timestamp,
 782                                  sizeof(timestamp), prp1, prp2);
 783 }
 784
 785 static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 786 {
 787     uint32_t dw10 = le32_to_cpu(cmd->cdw10);
 788     uint32_t result;
 789
 790     switch (dw10) {
 791     case NVME_VOLATILE_WRITE_CACHE:
 792         result = blk_enable_write_cache(n->conf.blk);
 793         trace_nvme_getfeat_vwcache(result ? "enabled" : "disabled");
 794         break;
 795     case NVME_NUMBER_OF_QUEUES:
 796         result = cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16));
 797         trace_nvme_getfeat_numq(result);
 798         break;
 799     case NVME_TIMESTAMP:
 800         return nvme_get_feature_timestamp(n, cmd);
 801         break;
 802     default:
 803         trace_nvme_err_invalid_getfeat(dw10);
 804         return NVME_INVALID_FIELD | NVME_DNR;
 805     }
 806
 807     req->cqe.result = result;
 808     return NVME_SUCCESS;
 809 }
 810
 811 static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd)
 812 {
 813     uint16_t ret;
 814     uint64_t timestamp;
 815     uint64_t prp1 = le64_to_cpu(cmd->prp1);
 816     uint64_t prp2 = le64_to_cpu(cmd->prp2);
 817
 818     ret = nvme_dma_write_prp(n, (uint8_t *)&timestamp,
 819                                 sizeof(timestamp), prp1, prp2);
 820     if (ret != NVME_SUCCESS) {
 821         return ret;
 822     }
 823
 824     nvme_set_timestamp(n, timestamp);
 825
 826     return NVME_SUCCESS;
 827 }
 828
 829 static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 830 {
 831     uint32_t dw10 = le32_to_cpu(cmd->cdw10);
 832     uint32_t dw11 = le32_to_cpu(cmd->cdw11);
 833
 834     switch (dw10) {
 835     case NVME_VOLATILE_WRITE_CACHE:
 836         blk_set_enable_write_cache(n->conf.blk, dw11 & 1);
 837         break;
 838     case NVME_NUMBER_OF_QUEUES:
 839         trace_nvme_setfeat_numq((dw11 & 0xFFFF) + 1,
 840                                 ((dw11 >> 16) & 0xFFFF) + 1,
 841                                 n->num_queues - 1, n->num_queues - 1);
 842         req->cqe.result =
 843             cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16));
 844         break;
 845
 846     case NVME_TIMESTAMP:
 847         return nvme_set_feature_timestamp(n, cmd);
 848         break;
 849
 850     default:
 851         trace_nvme_err_invalid_setfeat(dw10);
 852         return NVME_INVALID_FIELD | NVME_DNR;
 853     }
 854     return NVME_SUCCESS;
 855 }
 856
 857 static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req)
 858 {
 859     switch (cmd->opcode) {
 860     case NVME_ADM_CMD_DELETE_SQ:
 861         return nvme_del_sq(n, cmd);
 862     case NVME_ADM_CMD_CREATE_SQ:
 863         return nvme_create_sq(n, cmd);
 864     case NVME_ADM_CMD_DELETE_CQ:
 865         return nvme_del_cq(n, cmd);
 866     case NVME_ADM_CMD_CREATE_CQ:
 867         return nvme_create_cq(n, cmd);
 868     case NVME_ADM_CMD_IDENTIFY:
 869         return nvme_identify(n, cmd);
 870     case NVME_ADM_CMD_SET_FEATURES:
 871         return nvme_set_feature(n, cmd, req);
 872     case NVME_ADM_CMD_GET_FEATURES:
 873         return nvme_get_feature(n, cmd, req);
 874     default:
 875         trace_nvme_err_invalid_admin_opc(cmd->opcode);
 876         return NVME_INVALID_OPCODE | NVME_DNR;
 877     }
 878 }
 879
 880 static void nvme_process_sq(void *opaque)
 881 {
 882     NvmeSQueue *sq = opaque;
 883     NvmeCtrl *n = sq->ctrl;
 884     NvmeCQueue *cq = n->cq[sq->cqid];
 885
 886     uint16_t status;
 887     hwaddr addr;
 888     NvmeCmd cmd;
 889     NvmeRequest *req;
 890
 891     while (!(nvme_sq_empty(sq) || QTAILQ_EMPTY(&sq->req_list))) {
 892         addr = sq->dma_addr + sq->head * n->sqe_size;
 893         nvme_addr_read(n, addr, (void *)&cmd, sizeof(cmd));
 894         nvme_inc_sq_head(sq);
 895
 896         req = QTAILQ_FIRST(&sq->req_list);
 897         QTAILQ_REMOVE(&sq->req_list, req, entry);
 898         QTAILQ_INSERT_TAIL(&sq->out_req_list, req, entry);
 899         memset(&req->cqe, 0, sizeof(req->cqe));
 900         req->cqe.cid = cmd.cid;
 901
 902         status = sq->sqid ? nvme_io_cmd(n, &cmd, req) :
 903             nvme_admin_cmd(n, &cmd, req);
 904         if (status != NVME_NO_COMPLETE) {
 905             req->status = status;
 906             nvme_enqueue_req_completion(cq, req);
 907         }
 908     }
 909 }
 910
 911 static void nvme_clear_ctrl(NvmeCtrl *n)
 912 {
 913     int i;
 914
 915     blk_drain(n->conf.blk);
 916
 917     for (i = 0; i < n->num_queues; i++) {
 918         if (n->sq[i] != NULL) {
 919             nvme_free_sq(n->sq[i], n);
 920         }
 921     }
 922     for (i = 0; i < n->num_queues; i++) {
 923         if (n->cq[i] != NULL) {
 924             nvme_free_cq(n->cq[i], n);
 925         }
 926     }
 927
 928     blk_flush(n->conf.blk);
 929     n->bar.cc = 0;
 930 }
 931
 932 static int nvme_start_ctrl(NvmeCtrl *n)
 933 {
 934     uint32_t page_bits = NVME_CC_MPS(n->bar.cc) + 12;
 935     uint32_t page_size = 1 << page_bits;
 936
 937     if (unlikely(n->cq[0])) {
 938         trace_nvme_err_startfail_cq();
 939         return -1;
 940     }
 941     if (unlikely(n->sq[0])) {
 942         trace_nvme_err_startfail_sq();
 943         return -1;
 944     }
 945     if (unlikely(!n->bar.asq)) {
 946         trace_nvme_err_startfail_nbarasq();
 947         return -1;
 948     }
 949     if (unlikely(!n->bar.acq)) {
 950         trace_nvme_err_startfail_nbaracq();
 951         return -1;
 952     }
 953     if (unlikely(n->bar.asq & (page_size - 1))) {
 954         trace_nvme_err_startfail_asq_misaligned(n->bar.asq);
 955         return -1;
 956     }
 957     if (unlikely(n->bar.acq & (page_size - 1))) {
 958         trace_nvme_err_startfail_acq_misaligned(n->bar.acq);
 959         return -1;
 960     }
 961     if (unlikely(NVME_CC_MPS(n->bar.cc) <
 962                  NVME_CAP_MPSMIN(n->bar.cap))) {
 963         trace_nvme_err_startfail_page_too_small(
 964                     NVME_CC_MPS(n->bar.cc),
 965                     NVME_CAP_MPSMIN(n->bar.cap));
 966         return -1;
 967     }
 968     if (unlikely(NVME_CC_MPS(n->bar.cc) >
 969                  NVME_CAP_MPSMAX(n->bar.cap))) {
 970         trace_nvme_err_startfail_page_too_large(
 971                     NVME_CC_MPS(n->bar.cc),
 972                     NVME_CAP_MPSMAX(n->bar.cap));
 973         return -1;
 974     }
 975     if (unlikely(NVME_CC_IOCQES(n->bar.cc) <
 976                  NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) {
 977         trace_nvme_err_startfail_cqent_too_small(
 978                     NVME_CC_IOCQES(n->bar.cc),
 979                     NVME_CTRL_CQES_MIN(n->bar.cap));
 980         return -1;
 981     }
 982     if (unlikely(NVME_CC_IOCQES(n->bar.cc) >
 983                  NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) {
 984         trace_nvme_err_startfail_cqent_too_large(
 985                     NVME_CC_IOCQES(n->bar.cc),
 986                     NVME_CTRL_CQES_MAX(n->bar.cap));
 987         return -1;
 988     }
 989     if (unlikely(NVME_CC_IOSQES(n->bar.cc) <
 990                  NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) {
 991         trace_nvme_err_startfail_sqent_too_small(
 992                     NVME_CC_IOSQES(n->bar.cc),
 993                     NVME_CTRL_SQES_MIN(n->bar.cap));
 994         return -1;
 995     }
 996     if (unlikely(NVME_CC_IOSQES(n->bar.cc) >
 997                  NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) {
 998         trace_nvme_err_startfail_sqent_too_large(
 999                     NVME_CC_IOSQES(n->bar.cc),
1000                     NVME_CTRL_SQES_MAX(n->bar.cap));
1001         return -1;
1002     }
1003     if (unlikely(!NVME_AQA_ASQS(n->bar.aqa))) {
1004         trace_nvme_err_startfail_asqent_sz_zero();
1005         return -1;
1006     }
1007     if (unlikely(!NVME_AQA_ACQS(n->bar.aqa))) {
1008         trace_nvme_err_startfail_acqent_sz_zero();
1009         return -1;
1010     }
1011
1012     n->page_bits = page_bits;
1013     n->page_size = page_size;
1014     n->max_prp_ents = n->page_size / sizeof(uint64_t);
1015     n->cqe_size = 1 << NVME_CC_IOCQES(n->bar.cc);
1016     n->sqe_size = 1 << NVME_CC_IOSQES(n->bar.cc);
1017     nvme_init_cq(&n->admin_cq, n, n->bar.acq, 0, 0,
1018         NVME_AQA_ACQS(n->bar.aqa) + 1, 1);
1019     nvme_init_sq(&n->admin_sq, n, n->bar.asq, 0, 0,
1020         NVME_AQA_ASQS(n->bar.aqa) + 1);
1021
1022     nvme_set_timestamp(n, 0ULL);
1023
1024     return 0;
1025 }
1026
1027 static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
1028     unsigned size)
1029 {
1030     if (unlikely(offset & (sizeof(uint32_t) - 1))) {
1031         NVME_GUEST_ERR(nvme_ub_mmiowr_misaligned32,
1032                        "MMIO write not 32-bit aligned,"
1033                        " offset=0x%"PRIx64"", offset);
1034         /* should be ignored, fall through for now */
1035     }
1036
1037     if (unlikely(size < sizeof(uint32_t))) {
1038         NVME_GUEST_ERR(nvme_ub_mmiowr_toosmall,
1039                        "MMIO write smaller than 32-bits,"
1040                        " offset=0x%"PRIx64", size=%u",
1041                        offset, size);
1042         /* should be ignored, fall through for now */
1043     }
1044
1045     switch (offset) {
1046     case 0xc:   /* INTMS */
1047         if (unlikely(msix_enabled(&(n->parent_obj)))) {
1048             NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix,
1049                            "undefined access to interrupt mask set"
1050                            " when MSI-X is enabled");
1051             /* should be ignored, fall through for now */
1052         }
1053         n->bar.intms |= data & 0xffffffff;
1054         n->bar.intmc = n->bar.intms;
1055         trace_nvme_mmio_intm_set(data & 0xffffffff,
1056                                  n->bar.intmc);
1057         nvme_irq_check(n);
1058         break;
1059     case 0x10:  /* INTMC */
1060         if (unlikely(msix_enabled(&(n->parent_obj)))) {
1061             NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix,
1062                            "undefined access to interrupt mask clr"
1063                            " when MSI-X is enabled");
1064             /* should be ignored, fall through for now */
1065         }
1066         n->bar.intms &= ~(data & 0xffffffff);
1067         n->bar.intmc = n->bar.intms;
1068         trace_nvme_mmio_intm_clr(data & 0xffffffff,
1069                                  n->bar.intmc);
1070         nvme_irq_check(n);
1071         break;
1072     case 0x14:  /* CC */
1073         trace_nvme_mmio_cfg(data & 0xffffffff);
1074         /* Windows first sends data, then sends enable bit */
1075         if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) &&
1076             !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc))
1077         {
1078             n->bar.cc = data;
1079         }
1080
1081         if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) {
1082             n->bar.cc = data;
1083             if (unlikely(nvme_start_ctrl(n))) {
1084                 trace_nvme_err_startfail();
1085                 n->bar.csts = NVME_CSTS_FAILED;
1086             } else {
1087                 trace_nvme_mmio_start_success();
1088                 n->bar.csts = NVME_CSTS_READY;
1089             }
1090         } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) {
1091             trace_nvme_mmio_stopped();
1092             nvme_clear_ctrl(n);
1093             n->bar.csts &= ~NVME_CSTS_READY;
1094         }
1095         if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) {
1096             trace_nvme_mmio_shutdown_set();
1097             nvme_clear_ctrl(n);
1098             n->bar.cc = data;
1099             n->bar.csts |= NVME_CSTS_SHST_COMPLETE;
1100         } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) {
1101             trace_nvme_mmio_shutdown_cleared();
1102             n->bar.csts &= ~NVME_CSTS_SHST_COMPLETE;
1103             n->bar.cc = data;
1104         }
1105         break;
1106     case 0x1C:  /* CSTS */
1107         if (data & (1 << 4)) {
1108             NVME_GUEST_ERR(nvme_ub_mmiowr_ssreset_w1c_unsupported,
1109                            "attempted to W1C CSTS.NSSRO"
1110                            " but CAP.NSSRS is zero (not supported)");
1111         } else if (data != 0) {
1112             NVME_GUEST_ERR(nvme_ub_mmiowr_ro_csts,
1113                            "attempted to set a read only bit"
1114                            " of controller status");
1115         }
1116         break;
1117     case 0x20:  /* NSSR */
1118         if (data == 0x4E564D65) {
1119             trace_nvme_ub_mmiowr_ssreset_unsupported();
1120         } else {
1121             /* The spec says that writes of other values have no effect */
1122             return;
1123         }
1124         break;
1125     case 0x24:  /* AQA */
1126         n->bar.aqa = data & 0xffffffff;
1127         trace_nvme_mmio_aqattr(data & 0xffffffff);
1128         break;
1129     case 0x28:  /* ASQ */
1130         n->bar.asq = data;
1131         trace_nvme_mmio_asqaddr(data);
1132         break;
1133     case 0x2c:  /* ASQ hi */
1134         n->bar.asq |= data << 32;
1135         trace_nvme_mmio_asqaddr_hi(data, n->bar.asq);
1136         break;
1137     case 0x30:  /* ACQ */
1138         trace_nvme_mmio_acqaddr(data);
1139         n->bar.acq = data;
1140         break;
1141     case 0x34:  /* ACQ hi */
1142         n->bar.acq |= data << 32;
1143         trace_nvme_mmio_acqaddr_hi(data, n->bar.acq);
1144         break;
1145     case 0x38:  /* CMBLOC */
1146         NVME_GUEST_ERR(nvme_ub_mmiowr_cmbloc_reserved,
1147                        "invalid write to reserved CMBLOC"
1148                        " when CMBSZ is zero, ignored");
1149         return;
1150     case 0x3C:  /* CMBSZ */
1151         NVME_GUEST_ERR(nvme_ub_mmiowr_cmbsz_readonly,
1152                        "invalid write to read only CMBSZ, ignored");
1153         return;
1154     case 0xE00: /* PMRCAP */
1155         NVME_GUEST_ERR(nvme_ub_mmiowr_pmrcap_readonly,
1156                        "invalid write to PMRCAP register, ignored");
1157         return;
1158     case 0xE04: /* TODO PMRCTL */
1159         break;
1160     case 0xE08: /* PMRSTS */
1161         NVME_GUEST_ERR(nvme_ub_mmiowr_pmrsts_readonly,
1162                        "invalid write to PMRSTS register, ignored");
1163         return;
1164     case 0xE0C: /* PMREBS */
1165         NVME_GUEST_ERR(nvme_ub_mmiowr_pmrebs_readonly,
1166                        "invalid write to PMREBS register, ignored");
1167         return;
1168     case 0xE10: /* PMRSWTP */
1169         NVME_GUEST_ERR(nvme_ub_mmiowr_pmrswtp_readonly,
1170                        "invalid write to PMRSWTP register, ignored");
1171         return;
1172     case 0xE14: /* TODO PMRMSC */
1173          break;
1174     default:
1175         NVME_GUEST_ERR(nvme_ub_mmiowr_invalid,
1176                        "invalid MMIO write,"
1177                        " offset=0x%"PRIx64", data=%"PRIx64"",
1178                        offset, data);
1179         break;
1180     }
1181 }
1182
1183 static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
1184 {
1185     NvmeCtrl *n = (NvmeCtrl *)opaque;
1186     uint8_t *ptr = (uint8_t *)&n->bar;
1187     uint64_t val = 0;
1188
1189     if (unlikely(addr & (sizeof(uint32_t) - 1))) {
1190         NVME_GUEST_ERR(nvme_ub_mmiord_misaligned32,
1191                        "MMIO read not 32-bit aligned,"
1192                        " offset=0x%"PRIx64"", addr);
1193         /* should RAZ, fall through for now */
1194     } else if (unlikely(size < sizeof(uint32_t))) {
1195         NVME_GUEST_ERR(nvme_ub_mmiord_toosmall,
1196                        "MMIO read smaller than 32-bits,"
1197                        " offset=0x%"PRIx64"", addr);
1198         /* should RAZ, fall through for now */
1199     }
1200
1201     if (addr < sizeof(n->bar)) {
1202         /*
1203          * When PMRWBM bit 1 is set then read from
1204          * from PMRSTS should ensure prior writes
1205          * made it to persistent media
1206          */
1207         if (addr == 0xE08 &&
1208             (NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) {
1209             memory_region_msync(&n->pmrdev->mr, 0, n->pmrdev->size);
1210         }
1211         memcpy(&val, ptr + addr, size);
1212     } else {
1213         NVME_GUEST_ERR(nvme_ub_mmiord_invalid_ofs,
1214                        "MMIO read beyond last register,"
1215                        " offset=0x%"PRIx64", returning 0", addr);
1216     }
1217
1218     return val;
1219 }
1220
1221 static void nvme_process_db(NvmeCtrl *n, hwaddr addr, int val)
1222 {
1223     uint32_t qid;
1224
1225     if (unlikely(addr & ((1 << 2) - 1))) {
1226         NVME_GUEST_ERR(nvme_ub_db_wr_misaligned,
1227                        "doorbell write not 32-bit aligned,"
1228                        " offset=0x%"PRIx64", ignoring", addr);
1229         return;
1230     }
1231
1232     if (((addr - 0x1000) >> 2) & 1) {
1233         /* Completion queue doorbell write */
1234
1235         uint16_t new_head = val & 0xffff;
1236         int start_sqs;
1237         NvmeCQueue *cq;
1238
1239         qid = (addr - (0x1000 + (1 << 2))) >> 3;
1240         if (unlikely(nvme_check_cqid(n, qid))) {
1241             NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cq,
1242                            "completion queue doorbell write"
1243                            " for nonexistent queue,"
1244                            " sqid=%"PRIu32", ignoring", qid);
1245             return;
1246         }
1247
1248         cq = n->cq[qid];
1249         if (unlikely(new_head >= cq->size)) {
1250             NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cqhead,
1251                            "completion queue doorbell write value"
1252                            " beyond queue size, sqid=%"PRIu32","
1253                            " new_head=%"PRIu16", ignoring",
1254                            qid, new_head);
1255             return;
1256         }
1257
1258         start_sqs = nvme_cq_full(cq) ? 1 : 0;
1259         cq->head = new_head;
1260         if (start_sqs) {
1261             NvmeSQueue *sq;
1262             QTAILQ_FOREACH(sq, &cq->sq_list, entry) {
1263                 timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1264             }
1265             timer_mod(cq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1266         }
1267
1268         if (cq->tail == cq->head) {
1269             nvme_irq_deassert(n, cq);
1270         }
1271     } else {
1272         /* Submission queue doorbell write */
1273
1274         uint16_t new_tail = val & 0xffff;
1275         NvmeSQueue *sq;
1276
1277         qid = (addr - 0x1000) >> 3;
1278         if (unlikely(nvme_check_sqid(n, qid))) {
1279             NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sq,
1280                            "submission queue doorbell write"
1281                            " for nonexistent queue,"
1282                            " sqid=%"PRIu32", ignoring", qid);
1283             return;
1284         }
1285
1286         sq = n->sq[qid];
1287         if (unlikely(new_tail >= sq->size)) {
1288             NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sqtail,
1289                            "submission queue doorbell write value"
1290                            " beyond queue size, sqid=%"PRIu32","
1291                            " new_tail=%"PRIu16", ignoring",
1292                            qid, new_tail);
1293             return;
1294         }
1295
1296         sq->tail = new_tail;
1297         timer_mod(sq->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 500);
1298     }
1299 }
1300
1301 static void nvme_mmio_write(void *opaque, hwaddr addr, uint64_t data,
1302     unsigned size)
1303 {
1304     NvmeCtrl *n = (NvmeCtrl *)opaque;
1305     if (addr < sizeof(n->bar)) {
1306         nvme_write_bar(n, addr, data, size);
1307     } else if (addr >= 0x1000) {
1308         nvme_process_db(n, addr, data);
1309     }
1310 }
1311
1312 static const MemoryRegionOps nvme_mmio_ops = {
1313     .read = nvme_mmio_read,
1314     .write = nvme_mmio_write,
1315     .endianness = DEVICE_LITTLE_ENDIAN,
1316     .impl = {
1317         .min_access_size = 2,
1318         .max_access_size = 8,
1319     },
1320 };
1321
1322 static void nvme_cmb_write(void *opaque, hwaddr addr, uint64_t data,
1323     unsigned size)
1324 {
1325     NvmeCtrl *n = (NvmeCtrl *)opaque;
1326     stn_le_p(&n->cmbuf[addr], size, data);
1327 }
1328
1329 static uint64_t nvme_cmb_read(void *opaque, hwaddr addr, unsigned size)
1330 {
1331     NvmeCtrl *n = (NvmeCtrl *)opaque;
1332     return ldn_le_p(&n->cmbuf[addr], size);
1333 }
1334
1335 static const MemoryRegionOps nvme_cmb_ops = {
1336     .read = nvme_cmb_read,
1337     .write = nvme_cmb_write,
1338     .endianness = DEVICE_LITTLE_ENDIAN,
1339     .impl = {
1340         .min_access_size = 1,
1341         .max_access_size = 8,
1342     },
1343 };
1344
1345 static void nvme_realize(PCIDevice *pci_dev, Error **errp)
1346 {
1347     NvmeCtrl *n = NVME(pci_dev);
1348     NvmeIdCtrl *id = &n->id_ctrl;
1349
1350     int i;
1351     int64_t bs_size;
1352     uint8_t *pci_conf;
1353
1354     if (!n->num_queues) {
1355         error_setg(errp, "num_queues can't be zero");
1356         return;
1357     }
1358
1359     if (!n->conf.blk) {
1360         error_setg(errp, "drive property not set");
1361         return;
1362     }
1363
1364     bs_size = blk_getlength(n->conf.blk);
1365     if (bs_size < 0) {
1366         error_setg(errp, "could not get backing file size");
1367         return;
1368     }
1369
1370     if (!n->serial) {
1371         error_setg(errp, "serial property not set");
1372         return;
1373     }
1374
1375     if (!n->cmb_size_mb && n->pmrdev) {
1376         if (host_memory_backend_is_mapped(n->pmrdev)) {
1377             char *path = object_get_canonical_path_component(OBJECT(n->pmrdev));
1378             error_setg(errp, "can't use already busy memdev: %s", path);
1379             g_free(path);
1380             return;
1381         }
1382
1383         if (!is_power_of_2(n->pmrdev->size)) {
1384             error_setg(errp, "pmr backend size needs to be power of 2 in size");
1385             return;
1386         }
1387
1388         host_memory_backend_set_mapped(n->pmrdev, true);
1389     }
1390
1391     blkconf_blocksizes(&n->conf);
1392     if (!blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk),
1393                                        false, errp)) {
1394         return;
1395     }
1396
1397     pci_conf = pci_dev->config;
1398     pci_conf[PCI_INTERRUPT_PIN] = 1;
1399     pci_config_set_prog_interface(pci_dev->config, 0x2);
1400     pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS);
1401     pcie_endpoint_cap_init(pci_dev, 0x80);
1402
1403     n->num_namespaces = 1;
1404     n->reg_size = pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4);
1405     n->ns_size = bs_size / (uint64_t)n->num_namespaces;
1406
1407     n->namespaces = g_new0(NvmeNamespace, n->num_namespaces);
1408     n->sq = g_new0(NvmeSQueue *, n->num_queues);
1409     n->cq = g_new0(NvmeCQueue *, n->num_queues);
1410
1411     memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n,
1412                           "nvme", n->reg_size);
1413     pci_register_bar(pci_dev, 0,
1414         PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64,
1415         &n->iomem);
1416     msix_init_exclusive_bar(pci_dev, n->num_queues, 4, NULL);
1417
1418     id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
1419     id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
1420     strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
1421     strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' ');
1422     strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' ');
1423     id->rab = 6;
1424     id->ieee[0] = 0x00;
1425     id->ieee[1] = 0x02;
1426     id->ieee[2] = 0xb3;
1427     id->oacs = cpu_to_le16(0);
1428     id->frmw = 7 << 1;
1429     id->lpa = 1 << 0;
1430     id->sqes = (0x6 << 4) | 0x6;
1431     id->cqes = (0x4 << 4) | 0x4;
1432     id->nn = cpu_to_le32(n->num_namespaces);
1433     id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROS | NVME_ONCS_TIMESTAMP);
1434     id->psd[0].mp = cpu_to_le16(0x9c4);
1435     id->psd[0].enlat = cpu_to_le32(0x10);
1436     id->psd[0].exlat = cpu_to_le32(0x4);
1437     if (blk_enable_write_cache(n->conf.blk)) {
1438         id->vwc = 1;
1439     }
1440
1441     n->bar.cap = 0;
1442     NVME_CAP_SET_MQES(n->bar.cap, 0x7ff);
1443     NVME_CAP_SET_CQR(n->bar.cap, 1);
1444     NVME_CAP_SET_TO(n->bar.cap, 0xf);
1445     NVME_CAP_SET_CSS(n->bar.cap, 1);
1446     NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
1447
1448     n->bar.vs = 0x00010200;
1449     n->bar.intmc = n->bar.intms = 0;
1450
1451     if (n->cmb_size_mb) {
1452
1453         NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2);
1454         NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0);
1455
1456         NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1);
1457         NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0);
1458         NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0);
1459         NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1);
1460         NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1);
1461         NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */
1462         NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->cmb_size_mb);
1463
1464         n->cmbloc = n->bar.cmbloc;
1465         n->cmbsz = n->bar.cmbsz;
1466
1467         n->cmbuf = g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
1468         memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n,
1469                               "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz));
1470         pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc),
1471             PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
1472             PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem);
1473
1474     } else if (n->pmrdev) {
1475         /* Controller Capabilities register */
1476         NVME_CAP_SET_PMRS(n->bar.cap, 1);
1477
1478         /* PMR Capabities register */
1479         n->bar.pmrcap = 0;
1480         NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 0);
1481         NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 0);
1482         NVME_PMRCAP_SET_BIR(n->bar.pmrcap, 2);
1483         NVME_PMRCAP_SET_PMRTU(n->bar.pmrcap, 0);
1484         /* Turn on bit 1 support */
1485         NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
1486         NVME_PMRCAP_SET_PMRTO(n->bar.pmrcap, 0);
1487         NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 0);
1488
1489         /* PMR Control register */
1490         n->bar.pmrctl = 0;
1491         NVME_PMRCTL_SET_EN(n->bar.pmrctl, 0);
1492
1493         /* PMR Status register */
1494         n->bar.pmrsts = 0;
1495         NVME_PMRSTS_SET_ERR(n->bar.pmrsts, 0);
1496         NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 0);
1497         NVME_PMRSTS_SET_HSTS(n->bar.pmrsts, 0);
1498         NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 0);
1499
1500         /* PMR Elasticity Buffer Size register */
1501         n->bar.pmrebs = 0;
1502         NVME_PMREBS_SET_PMRSZU(n->bar.pmrebs, 0);
1503         NVME_PMREBS_SET_RBB(n->bar.pmrebs, 0);
1504         NVME_PMREBS_SET_PMRWBZ(n->bar.pmrebs, 0);
1505
1506         /* PMR Sustained Write Throughput register */
1507         n->bar.pmrswtp = 0;
1508         NVME_PMRSWTP_SET_PMRSWTU(n->bar.pmrswtp, 0);
1509         NVME_PMRSWTP_SET_PMRSWTV(n->bar.pmrswtp, 0);
1510
1511         /* PMR Memory Space Control register */
1512         n->bar.pmrmsc = 0;
1513         NVME_PMRMSC_SET_CMSE(n->bar.pmrmsc, 0);
1514         NVME_PMRMSC_SET_CBA(n->bar.pmrmsc, 0);
1515
1516         pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
1517             PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 |
1518             PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
1519     }
1520
1521     for (i = 0; i < n->num_namespaces; i++) {
1522         NvmeNamespace *ns = &n->namespaces[i];
1523         NvmeIdNs *id_ns = &ns->id_ns;
1524         id_ns->nsfeat = 0;
1525         id_ns->nlbaf = 0;
1526         id_ns->flbas = 0;
1527         id_ns->mc = 0;
1528         id_ns->dpc = 0;
1529         id_ns->dps = 0;
1530         id_ns->lbaf[0].ds = BDRV_SECTOR_BITS;
1531         id_ns->ncap  = id_ns->nuse = id_ns->nsze =
1532             cpu_to_le64(n->ns_size >>
1533                 id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas)].ds);
1534     }
1535 }
1536
1537 static void nvme_exit(PCIDevice *pci_dev)
1538 {
1539     NvmeCtrl *n = NVME(pci_dev);
1540
1541     nvme_clear_ctrl(n);
1542     g_free(n->namespaces);
1543     g_free(n->cq);
1544     g_free(n->sq);
1545
1546     if (n->cmb_size_mb) {
1547         g_free(n->cmbuf);
1548     }
1549
1550     if (n->pmrdev) {
1551         host_memory_backend_set_mapped(n->pmrdev, false);
1552     }
1553     msix_uninit_exclusive_bar(pci_dev);
1554 }
1555
1556 static Property nvme_props[] = {
1557     DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf),
1558     DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND,
1559                      HostMemoryBackend *),
1560     DEFINE_PROP_STRING("serial", NvmeCtrl, serial),
1561     DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0),
1562     DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64),
1563     DEFINE_PROP_END_OF_LIST(),
1564 };
1565
1566 static const VMStateDescription nvme_vmstate = {
1567     .name = "nvme",
1568     .unmigratable = 1,
1569 };
1570
1571 static void nvme_class_init(ObjectClass *oc, void *data)
1572 {
1573     DeviceClass *dc = DEVICE_CLASS(oc);
1574     PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
1575
1576     pc->realize = nvme_realize;
1577     pc->exit = nvme_exit;
1578     pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
1579     pc->vendor_id = PCI_VENDOR_ID_INTEL;
1580     pc->device_id = 0x5845;
1581     pc->revision = 2;
1582
1583     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1584     dc->desc = "Non-Volatile Memory Express";
1585     device_class_set_props(dc, nvme_props);
1586     dc->vmsd = &nvme_vmstate;
1587 }
1588
1589 static void nvme_instance_init(Object *obj)
1590 {
1591     NvmeCtrl *s = NVME(obj);
1592
1593     device_add_bootindex_property(obj, &s->conf.bootindex,
1594                                   "bootindex", "/namespace@1,0",
1595                                   DEVICE(obj));
1596 }
1597
1598 static const TypeInfo nvme_info = {
1599     .name          = TYPE_NVME,
1600     .parent        = TYPE_PCI_DEVICE,
1601     .instance_size = sizeof(NvmeCtrl),
1602     .class_init    = nvme_class_init,
1603     .instance_init = nvme_instance_init,
1604     .interfaces = (InterfaceInfo[]) {
1605         { INTERFACE_PCIE_DEVICE },
1606         { }
1607     },
1608 };
1609
1610 static void nvme_register_types(void)
1611 {
1612     type_register_static(&nvme_info);
1613 }
1614
1615 type_init(nvme_register_types)