target-sh4/cpu.c

   1 /*
   2  * QEMU SuperH CPU
   3  *
   4  * Copyright (c) 2005 Samuel Tardieu
   5  * Copyright (c) 2012 SUSE LINUX Products GmbH
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see
  19  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  20  */
  21
  22 #include "cpu.h"
  23 #include "qemu-common.h"
  24 #include "migration/vmstate.h"
  25
  26
  27 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
  28 {
  29     SuperHCPU *cpu = SUPERH_CPU(cs);
  30
  31     cpu->env.pc = value;
  32 }
  33
  34 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  35 {
  36     SuperHCPU *cpu = SUPERH_CPU(cs);
  37
  38     cpu->env.pc = tb->pc;
  39     cpu->env.flags = tb->flags;
  40 }
  41
  42 static bool superh_cpu_has_work(CPUState *cs)
  43 {
  44     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  45 }
  46
  47 /* CPUClass::reset() */
  48 static void superh_cpu_reset(CPUState *s)
  49 {
  50     SuperHCPU *cpu = SUPERH_CPU(s);
  51     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
  52     CPUSH4State *env = &cpu->env;
  53
  54     scc->parent_reset(s);
  55
  56     memset(env, 0, offsetof(CPUSH4State, id));
  57     tlb_flush(s, 1);
  58
  59     env->pc = 0xA0000000;
  60 #if defined(CONFIG_USER_ONLY)
  61     env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
  62     set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
  63 #else
  64     env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
  65               (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
  66     env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
  67     set_float_rounding_mode(float_round_to_zero, &env->fp_status);
  68     set_flush_to_zero(1, &env->fp_status);
  69 #endif
  70     set_default_nan_mode(1, &env->fp_status);
  71 }
  72
  73 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
  74 {
  75     info->mach = bfd_mach_sh4;
  76     info->print_insn = print_insn_sh;
  77 }
  78
  79 typedef struct SuperHCPUListState {
  80     fprintf_function cpu_fprintf;
  81     FILE *file;
  82 } SuperHCPUListState;
  83
  84 /* Sort alphabetically by type name. */
  85 static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
  86 {
  87     ObjectClass *class_a = (ObjectClass *)a;
  88     ObjectClass *class_b = (ObjectClass *)b;
  89     const char *name_a, *name_b;
  90
  91     name_a = object_class_get_name(class_a);
  92     name_b = object_class_get_name(class_b);
  93     return strcmp(name_a, name_b);
  94 }
  95
  96 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
  97 {
  98     ObjectClass *oc = data;
  99     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 100     SuperHCPUListState *s = user_data;
 101
 102     (*s->cpu_fprintf)(s->file, "%s\n",
 103                       scc->name);
 104 }
 105
 106 void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 107 {
 108     SuperHCPUListState s = {
 109         .cpu_fprintf = cpu_fprintf,
 110         .file = f,
 111     };
 112     GSList *list;
 113
 114     list = object_class_get_list(TYPE_SUPERH_CPU, false);
 115     list = g_slist_sort(list, superh_cpu_list_compare);
 116     g_slist_foreach(list, superh_cpu_list_entry, &s);
 117     g_slist_free(list);
 118 }
 119
 120 static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
 121 {
 122     const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
 123     const char *name = b;
 124
 125     return strcasecmp(scc->name, name);
 126 }
 127
 128 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
 129 {
 130     ObjectClass *oc;
 131     GSList *list, *item;
 132
 133     if (cpu_model == NULL) {
 134         return NULL;
 135     }
 136     if (strcasecmp(cpu_model, "any") == 0) {
 137         return object_class_by_name(TYPE_SH7750R_CPU);
 138     }
 139
 140     oc = object_class_by_name(cpu_model);
 141     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
 142         && !object_class_is_abstract(oc)) {
 143         return oc;
 144     }
 145
 146     oc = NULL;
 147     list = object_class_get_list(TYPE_SUPERH_CPU, false);
 148     item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
 149     if (item != NULL) {
 150         oc = item->data;
 151     }
 152     g_slist_free(list);
 153     return oc;
 154 }
 155
 156 SuperHCPU *cpu_sh4_init(const char *cpu_model)
 157 {
 158     return SUPERH_CPU(cpu_generic_init(TYPE_SUPERH_CPU, cpu_model));
 159 }
 160
 161 static void sh7750r_cpu_initfn(Object *obj)
 162 {
 163     SuperHCPU *cpu = SUPERH_CPU(obj);
 164     CPUSH4State *env = &cpu->env;
 165
 166     env->id = SH_CPU_SH7750R;
 167     env->features = SH_FEATURE_BCR3_AND_BCR4;
 168 }
 169
 170 static void sh7750r_class_init(ObjectClass *oc, void *data)
 171 {
 172     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 173
 174     scc->name = "SH7750R";
 175     scc->pvr = 0x00050000;
 176     scc->prr = 0x00000100;
 177     scc->cvr = 0x00110000;
 178 }
 179
 180 static const TypeInfo sh7750r_type_info = {
 181     .name = TYPE_SH7750R_CPU,
 182     .parent = TYPE_SUPERH_CPU,
 183     .class_init = sh7750r_class_init,
 184     .instance_init = sh7750r_cpu_initfn,
 185 };
 186
 187 static void sh7751r_cpu_initfn(Object *obj)
 188 {
 189     SuperHCPU *cpu = SUPERH_CPU(obj);
 190     CPUSH4State *env = &cpu->env;
 191
 192     env->id = SH_CPU_SH7751R;
 193     env->features = SH_FEATURE_BCR3_AND_BCR4;
 194 }
 195
 196 static void sh7751r_class_init(ObjectClass *oc, void *data)
 197 {
 198     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 199
 200     scc->name = "SH7751R";
 201     scc->pvr = 0x04050005;
 202     scc->prr = 0x00000113;
 203     scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
 204 }
 205
 206 static const TypeInfo sh7751r_type_info = {
 207     .name = TYPE_SH7751R_CPU,
 208     .parent = TYPE_SUPERH_CPU,
 209     .class_init = sh7751r_class_init,
 210     .instance_init = sh7751r_cpu_initfn,
 211 };
 212
 213 static void sh7785_cpu_initfn(Object *obj)
 214 {
 215     SuperHCPU *cpu = SUPERH_CPU(obj);
 216     CPUSH4State *env = &cpu->env;
 217
 218     env->id = SH_CPU_SH7785;
 219     env->features = SH_FEATURE_SH4A;
 220 }
 221
 222 static void sh7785_class_init(ObjectClass *oc, void *data)
 223 {
 224     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 225
 226     scc->name = "SH7785";
 227     scc->pvr = 0x10300700;
 228     scc->prr = 0x00000200;
 229     scc->cvr = 0x71440211;
 230 }
 231
 232 static const TypeInfo sh7785_type_info = {
 233     .name = TYPE_SH7785_CPU,
 234     .parent = TYPE_SUPERH_CPU,
 235     .class_init = sh7785_class_init,
 236     .instance_init = sh7785_cpu_initfn,
 237 };
 238
 239 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
 240 {
 241     CPUState *cs = CPU(dev);
 242     SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
 243
 244     cpu_reset(cs);
 245     qemu_init_vcpu(cs);
 246
 247     scc->parent_realize(dev, errp);
 248 }
 249
 250 static void superh_cpu_initfn(Object *obj)
 251 {
 252     CPUState *cs = CPU(obj);
 253     SuperHCPU *cpu = SUPERH_CPU(obj);
 254     CPUSH4State *env = &cpu->env;
 255
 256     cs->env_ptr = env;
 257     cpu_exec_init(cs, &error_abort);
 258
 259     env->movcal_backup_tail = &(env->movcal_backup);
 260
 261     if (tcg_enabled()) {
 262         sh4_translate_init();
 263     }
 264 }
 265
 266 static const VMStateDescription vmstate_sh_cpu = {
 267     .name = "cpu",
 268     .unmigratable = 1,
 269 };
 270
 271 static void superh_cpu_class_init(ObjectClass *oc, void *data)
 272 {
 273     DeviceClass *dc = DEVICE_CLASS(oc);
 274     CPUClass *cc = CPU_CLASS(oc);
 275     SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
 276
 277     scc->parent_realize = dc->realize;
 278     dc->realize = superh_cpu_realizefn;
 279
 280     scc->parent_reset = cc->reset;
 281     cc->reset = superh_cpu_reset;
 282
 283     cc->class_by_name = superh_cpu_class_by_name;
 284     cc->has_work = superh_cpu_has_work;
 285     cc->do_interrupt = superh_cpu_do_interrupt;
 286     cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
 287     cc->dump_state = superh_cpu_dump_state;
 288     cc->set_pc = superh_cpu_set_pc;
 289     cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
 290     cc->gdb_read_register = superh_cpu_gdb_read_register;
 291     cc->gdb_write_register = superh_cpu_gdb_write_register;
 292 #ifdef CONFIG_USER_ONLY
 293     cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
 294 #else
 295     cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
 296 #endif
 297     cc->disas_set_info = superh_cpu_disas_set_info;
 298
 299     cc->gdb_num_core_regs = 59;
 300
 301     dc->vmsd = &vmstate_sh_cpu;
 302
 303     /*
 304      * Reason: superh_cpu_initfn() calls cpu_exec_init(), which saves
 305      * the object in cpus -> dangling pointer after final
 306      * object_unref().
 307      */
 308     dc->cannot_destroy_with_object_finalize_yet = true;
 309 }
 310
 311 static const TypeInfo superh_cpu_type_info = {
 312     .name = TYPE_SUPERH_CPU,
 313     .parent = TYPE_CPU,
 314     .instance_size = sizeof(SuperHCPU),
 315     .instance_init = superh_cpu_initfn,
 316     .abstract = true,
 317     .class_size = sizeof(SuperHCPUClass),
 318     .class_init = superh_cpu_class_init,
 319 };
 320
 321 static void superh_cpu_register_types(void)
 322 {
 323     type_register_static(&superh_cpu_type_info);
 324     type_register_static(&sh7750r_type_info);
 325     type_register_static(&sh7751r_type_info);
 326     type_register_static(&sh7785_type_info);
 327 }
 328
 329 type_init(superh_cpu_register_types)