hw/lm32_boards.c

   1 /*
   2  *  QEMU models for LatticeMico32 uclinux and evr32 boards.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <[email protected]>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "sysbus.h"
  21 #include "hw.h"
  22 #include "net.h"
  23 #include "flash.h"
  24 #include "devices.h"
  25 #include "boards.h"
  26 #include "loader.h"
  27 #include "blockdev.h"
  28 #include "elf.h"
  29 #include "lm32_hwsetup.h"
  30 #include "lm32.h"
  31 #include "exec-memory.h"
  32
  33 typedef struct {
  34     LM32CPU *cpu;
  35     target_phys_addr_t bootstrap_pc;
  36     target_phys_addr_t flash_base;
  37     target_phys_addr_t hwsetup_base;
  38     target_phys_addr_t initrd_base;
  39     size_t initrd_size;
  40     target_phys_addr_t cmdline_base;
  41 } ResetInfo;
  42
  43 static void cpu_irq_handler(void *opaque, int irq, int level)
  44 {
  45     CPULM32State *env = opaque;
  46
  47     if (level) {
  48         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  49     } else {
  50         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  51     }
  52 }
  53
  54 static void main_cpu_reset(void *opaque)
  55 {
  56     ResetInfo *reset_info = opaque;
  57     CPULM32State *env = &reset_info->cpu->env;
  58
  59     cpu_reset(CPU(reset_info->cpu));
  60
  61     /* init defaults */
  62     env->pc = (uint32_t)reset_info->bootstrap_pc;
  63     env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
  64     env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
  65     env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
  66     env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
  67         reset_info->initrd_size);
  68     env->eba = reset_info->flash_base;
  69     env->deba = reset_info->flash_base;
  70 }
  71
  72 static void lm32_evr_init(QEMUMachineInitArgs *args)
  73 {
  74     const char *cpu_model = args->cpu_model;
  75     const char *kernel_filename = args->kernel_filename;
  76     LM32CPU *cpu;
  77     CPULM32State *env;
  78     DriveInfo *dinfo;
  79     MemoryRegion *address_space_mem =  get_system_memory();
  80     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
  81     qemu_irq *cpu_irq, irq[32];
  82     ResetInfo *reset_info;
  83     int i;
  84
  85     /* memory map */
  86     target_phys_addr_t flash_base  = 0x04000000;
  87     size_t flash_sector_size       = 256 * 1024;
  88     size_t flash_size              = 32 * 1024 * 1024;
  89     target_phys_addr_t ram_base    = 0x08000000;
  90     size_t ram_size                = 64 * 1024 * 1024;
  91     target_phys_addr_t timer0_base = 0x80002000;
  92     target_phys_addr_t uart0_base  = 0x80006000;
  93     target_phys_addr_t timer1_base = 0x8000a000;
  94     int uart0_irq                  = 0;
  95     int timer0_irq                 = 1;
  96     int timer1_irq                 = 3;
  97
  98     reset_info = g_malloc0(sizeof(ResetInfo));
  99
 100     if (cpu_model == NULL) {
 101         cpu_model = "lm32-full";
 102     }
 103     cpu = cpu_lm32_init(cpu_model);
 104     env = &cpu->env;
 105     reset_info->cpu = cpu;
 106
 107     reset_info->flash_base = flash_base;
 108
 109     memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
 110     vmstate_register_ram_global(phys_ram);
 111     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 112
 113     dinfo = drive_get(IF_PFLASH, 0, 0);
 114     /* Spansion S29NS128P */
 115     pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
 116                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
 117                           flash_size / flash_sector_size, 1, 2,
 118                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 119
 120     /* create irq lines */
 121     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
 122     env->pic_state = lm32_pic_init(*cpu_irq);
 123     for (i = 0; i < 32; i++) {
 124         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 125     }
 126
 127     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 128     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 129     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 130
 131     /* make sure juart isn't the first chardev */
 132     env->juart_state = lm32_juart_init();
 133
 134     reset_info->bootstrap_pc = flash_base;
 135
 136     if (kernel_filename) {
 137         uint64_t entry;
 138         int kernel_size;
 139
 140         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 141                                1, ELF_MACHINE, 0);
 142         reset_info->bootstrap_pc = entry;
 143
 144         if (kernel_size < 0) {
 145             kernel_size = load_image_targphys(kernel_filename, ram_base,
 146                                               ram_size);
 147             reset_info->bootstrap_pc = ram_base;
 148         }
 149
 150         if (kernel_size < 0) {
 151             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 152                     kernel_filename);
 153             exit(1);
 154         }
 155     }
 156
 157     qemu_register_reset(main_cpu_reset, reset_info);
 158 }
 159
 160 static void lm32_uclinux_init(QEMUMachineInitArgs *args)
 161 {
 162     const char *cpu_model = args->cpu_model;
 163     const char *kernel_filename = args->kernel_filename;
 164     const char *kernel_cmdline = args->kernel_cmdline;
 165     const char *initrd_filename = args->initrd_filename;
 166     LM32CPU *cpu;
 167     CPULM32State *env;
 168     DriveInfo *dinfo;
 169     MemoryRegion *address_space_mem =  get_system_memory();
 170     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
 171     qemu_irq *cpu_irq, irq[32];
 172     HWSetup *hw;
 173     ResetInfo *reset_info;
 174     int i;
 175
 176     /* memory map */
 177     target_phys_addr_t flash_base   = 0x04000000;
 178     size_t flash_sector_size        = 256 * 1024;
 179     size_t flash_size               = 32 * 1024 * 1024;
 180     target_phys_addr_t ram_base     = 0x08000000;
 181     size_t ram_size                 = 64 * 1024 * 1024;
 182     target_phys_addr_t uart0_base   = 0x80000000;
 183     target_phys_addr_t timer0_base  = 0x80002000;
 184     target_phys_addr_t timer1_base  = 0x80010000;
 185     target_phys_addr_t timer2_base  = 0x80012000;
 186     int uart0_irq                   = 0;
 187     int timer0_irq                  = 1;
 188     int timer1_irq                  = 20;
 189     int timer2_irq                  = 21;
 190     target_phys_addr_t hwsetup_base = 0x0bffe000;
 191     target_phys_addr_t cmdline_base = 0x0bfff000;
 192     target_phys_addr_t initrd_base  = 0x08400000;
 193     size_t initrd_max               = 0x01000000;
 194
 195     reset_info = g_malloc0(sizeof(ResetInfo));
 196
 197     if (cpu_model == NULL) {
 198         cpu_model = "lm32-full";
 199     }
 200     cpu = cpu_lm32_init(cpu_model);
 201     env = &cpu->env;
 202     reset_info->cpu = cpu;
 203
 204     reset_info->flash_base = flash_base;
 205
 206     memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
 207     vmstate_register_ram_global(phys_ram);
 208     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 209
 210     dinfo = drive_get(IF_PFLASH, 0, 0);
 211     /* Spansion S29NS128P */
 212     pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
 213                           dinfo ? dinfo->bdrv : NULL, flash_sector_size,
 214                           flash_size / flash_sector_size, 1, 2,
 215                           0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 216
 217     /* create irq lines */
 218     cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
 219     env->pic_state = lm32_pic_init(*cpu_irq);
 220     for (i = 0; i < 32; i++) {
 221         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 222     }
 223
 224     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 225     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 226     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 227     sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
 228
 229     /* make sure juart isn't the first chardev */
 230     env->juart_state = lm32_juart_init();
 231
 232     reset_info->bootstrap_pc = flash_base;
 233
 234     if (kernel_filename) {
 235         uint64_t entry;
 236         int kernel_size;
 237
 238         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 239                                1, ELF_MACHINE, 0);
 240         reset_info->bootstrap_pc = entry;
 241
 242         if (kernel_size < 0) {
 243             kernel_size = load_image_targphys(kernel_filename, ram_base,
 244                                               ram_size);
 245             reset_info->bootstrap_pc = ram_base;
 246         }
 247
 248         if (kernel_size < 0) {
 249             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 250                     kernel_filename);
 251             exit(1);
 252         }
 253     }
 254
 255     /* generate a rom with the hardware description */
 256     hw = hwsetup_init();
 257     hwsetup_add_cpu(hw, "LM32", 75000000);
 258     hwsetup_add_flash(hw, "flash", flash_base, flash_size);
 259     hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
 260     hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
 261     hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
 262     hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
 263     hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
 264     hwsetup_add_trailer(hw);
 265     hwsetup_create_rom(hw, hwsetup_base);
 266     hwsetup_free(hw);
 267
 268     reset_info->hwsetup_base = hwsetup_base;
 269
 270     if (kernel_cmdline && strlen(kernel_cmdline)) {
 271         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 272                 kernel_cmdline);
 273         reset_info->cmdline_base = cmdline_base;
 274     }
 275
 276     if (initrd_filename) {
 277         size_t initrd_size;
 278         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 279                 initrd_max);
 280         reset_info->initrd_base = initrd_base;
 281         reset_info->initrd_size = initrd_size;
 282     }
 283
 284     qemu_register_reset(main_cpu_reset, reset_info);
 285 }
 286
 287 static QEMUMachine lm32_evr_machine = {
 288     .name = "lm32-evr",
 289     .desc = "LatticeMico32 EVR32 eval system",
 290     .init = lm32_evr_init,
 291     .is_default = 1
 292 };
 293
 294 static QEMUMachine lm32_uclinux_machine = {
 295     .name = "lm32-uclinux",
 296     .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
 297     .init = lm32_uclinux_init,
 298     .is_default = 0
 299 };
 300
 301 static void lm32_machine_init(void)
 302 {
 303     qemu_register_machine(&lm32_uclinux_machine);
 304     qemu_register_machine(&lm32_evr_machine);
 305 }
 306
 307 machine_init(lm32_machine_init);